🤖 AI Summary
This work addresses the challenge of efficiently executing Monte Carlo Tree Search (MCTS) on edge devices, where conventional processors incur high power consumption (55–300 W) and in-memory computing (IMC) architectures struggle with MCTS’s irregular, multi-stage nature. The authors propose a “phase-to-primitive decomposition” methodology that maps MCTS’s selection, expansion, simulation, and backpropagation phases onto hardware-native IMC primitives, enabling the first unified IMC implementation of MCTS. Fabricated in 22 nm technology, the proposed multi-primitive IMC chip integrates content-addressable memory, combinational logic, and RRAM/SRAM crossbar arrays. Evaluated on a 9×9 Go task, it achieves an energy efficiency of approximately 60 mW—96× better than a CPU and 65–2,059× better than an H100 GPU—while matching the playing strength of open-source Go engines rated by the European Go Federation.
📝 Abstract
Monte Carlo tree search (MCTS) enables artificial intelligence (AI) decision-making, but requires 55-300 W on conventional processors, limiting edge deployment. In-memory computing (IMC) is energy-efficient on regular workloads but has been considered incompatible with irregular multi-phase algorithms. We introduce phase-to-primitive decomposition, which reformulates each algorithmic phase as a hardware-native IMC primitive. Applied to MCTS, selection, expansion, rollout and backpropagation map to content-addressable memory, combinational logic, a resistive random-access memory (RRAM) crossbar and static random-access memory, keeping search on chip. At 22 nm with fabricated RRAM-array parameters, IMC-MCTS consumes ~60 mW for 9x9 Go, achieving 96x energy efficiency over a central processing unit (CPU) and 65x-2,059x over an H100 graphics processing unit (GPU). It reaches a European Go Federation rating within sample-size uncertainty of open-source Go engines (Pachi-UCT and Michi-C). The same substrate runs eight applications across four AI domains.