PIMID: A Full-System Simulator with Intricacy and Diversity for Processing-in-Memory

2026-07-27

AI Summary

This work addresses the limited design space of existing Processing-in-Memory (PIM) simulators, which struggle to support diverse memory technologies, flexible processing element (PE) deployment, and end-to-end evaluation. To overcome these limitations, we present PIMID—the first full-system PIM simulator within a unified framework—integrating execution-driven and trace-driven methodologies. PIMID supports eleven memory technologies (including DRAM, SRAM, and non-volatile memories), configurable PE placement and scale, and compatibility with both OpenMP shared-memory and MPI message-passing programming models. It provides fine-grained latency and energy breakdowns and features a YAML-based plugin mechanism for future extensibility. Experimental results reveal that memory technology impacts performance by over an order of magnitude, with the best conventional main memory not necessarily optimal as a PIM substrate; regular kernels exhibit superlinear performance scaling with PE count; graph traversal is bottlenecked by MPI communication; and shared-memory offloading on HBM3 achieves both energy efficiency and end-to-end speedup.

Abstract

Processing-in-Memory addresses the memory wall by co-locating computation with memory, but because real PIM hardware remains scarce, simulation is the primary way to explore the PIM design space. Yet existing PIM simulators each cover only part of that space: they typically model a single memory technology, fix processing elements at one level of the memory hierarchy, support a single execution model, and stop at the device boundary. We therefore present PIMID, an execution- and trace-driven full-system simulator that closes these gaps in one tool. PIMID supports both the shared-memory and message-passing execution models, running annotated parallel code in OpenMP and MPI side by side across eleven memory technologies (seven DRAM standards, SRAM, and three non-volatile memories); it places PEs anywhere from subarrays to logic dies, sweeps PE count and core-model fidelity, and prices the in-memory network per technology from measured congestion. Its single-process host-device co-simulation resolves an end-to-end time and energy breakdown (host preparation, device compute, and explicit boundary charges) that device-only tools cannot produce. Across the resulting dual-execution-model dataset, PIMID shows that the memory technology alone moves execution time by more than an order of magnitude and that the best host main memory is not the best PIM substrate; that regular kernels scale superlinearly with PE count as in-memory bandwidth co-scales with compute; that graph traversal under message-passing hits a collective-communication wall absent under shared memory; and that at full-system scope the offload trades time for energy only on the bandwidth-class memory: shared-memory offload saves energy on HBM3 while a 16-core host keeps every end-to-end time win. PIMID's plugin interfaces let new engines and models be added through standardized YAML specifications as PIM technology evolves.

Problem

• Processing-in-Memory
• full-system simulation
• memory technology
• execution model
• design space exploration

Innovation

• Processing-in-Memory
• Full-system simulation
• Execution model diversity
• Memory technology heterogeneity
• Host-device co-simulation