DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation

2026-07-27

AI Summary

This work addresses the limitations of existing chiplet simulation tools, which typically employ fixed-latency models that oversimplify interconnect behavior and neglect the impact of physical-layer dynamics on system performance. For the first time in gem5, this study implements a runtime, end-to-end high-fidelity PHY model for chiplet interconnects, incorporating key techniques such as QC-LDPC encoding/decoding, PAM4 modulation, LLR demodulation, adaptive retransmission, and PHY-level flow control. The model accurately captures the effects of noise, crosstalk, channel loss, and load variations on communication reliability and latency. By integrating these physical-layer characteristics into system-level simulation, the proposed approach significantly enhances simulation fidelity and effectively mitigates inaccuracies in high-level performance metrics—such as IPC—that arise from ignoring dynamic PHY behaviors.

Abstract

Scaling monolithic multicores is increasingly constrained by power/thermal limits, yield, and rising manufacturing and testing costs. Chiplet designs address these challenges by partitioning large dies into smaller parts (typically multiple core-complex dies and an I/O die) linked via high-bandwidth physical fabrics (PHY). As bandwidth and wiring density scale, however, these short-reach links are pushed closer to their signal-integrity limits, increasing susceptibility to noise, crosstalk, and channel loss, motivating stronger link-level reliability mechanisms such as forward error correction (FEC). Despite this trend, state-of-the-art simulation infrastructures often approximate inter-chiplet links using oversimplified, fixed-latency models. Such abstractions overlook the inherently dynamic, runtime-dependent behavior of the PHY -- including channel conditions (e.g., signal-to-noise ratio shifts, signal crosstalk, clock jitter), iterative decoder convergence and packet retransmissions, and application dynamics (e.g., LLC-misses that travel across chiplet boundaries) -- all of which are hard to determine offline. We show that neglecting these effects distorts inter-chiplet packet-level timing and high-level performance metrics such as IPC, leading to off-trend simulation results. We present DICE, an in-simulation, runtime PHY modeling in gem5 that captures the end-to-end inter-chiplet datapath, including QC-LDPC encoding/decoding, PAM4 modulation, lossy-channel transmission, LLR-based demodulation, adaptive packet re-sending, and PHY-level flow control between chiplets.

Problem

• chiplet
• PHY modeling
• signal integrity
• simulation accuracy
• inter-chiplet communication

Innovation

• chiplet
• PHY modeling
• runtime simulation
• forward error correction
• inter-chiplet communication