The SpiNNaker2 chip: a many-core platform for flexible and scalable brain-inspired computing

2026-07-27

AI Summary

This work addresses the challenges of energy efficiency, flexibility, and scalability in integrating brain-inspired computing with deep learning by designing and implementing the SpiNNaker2 chip, which for the first time unifies large-scale spiking neural network simulation and high-efficiency deep learning on a single die. The chip integrates 152 ARM Cortex-M4F cores, dedicated neuromorphic accelerators, and an extended event-driven routing fabric, complemented by high-speed interfaces including LPDDR4 and Gigabit Ethernet. Experimental results demonstrate an INT8 deep learning throughput of 4.5 TOPS at an energy efficiency of 2.7 TOPS/W, capable of simulating over 150,000 neurons and 1.8 billion synaptic events per second, while maintaining a standby power consumption below 250 mW.

Abstract

In deep learning, efficiency gets more and more important to compensate for the ongoing growth in model sizes and applications. Neuromorphic hardware has long been advocated as an upcoming alternative to deep networks, taking inspiration from the brain for achieving unprecedented energy efficiency. However, demonstrations of these gains only recently began to grow in complexity and real-world applicability. With SpiNNaker2, we present a chip that bridges the gap between deep networks and neuromorphic computing and allows for flexible exploration of computing approaches that combine both worlds. It features 152 processing elements equipped with an ARM M4F processor and dedicated accelerators, an extended SpiNNaker routing fabric for scalable event-based communication and a range of external interfaces for system integration, including Gbit Ethernet and an LPDDR4 memory interface. We demonstrate performance and efficiency of the SpiNNaker2 chip for neuromorphic and deep network workloads, as well as novel event-based computing approaches. For deep network workloads, the chip achieves up to 4.5 TOPS in high performance mode and up to 2.7 TOPS/W efficiency in high efficiency mode for INT8 workloads. The chip supports spiking neural networks with >150000 neurons and >1.8 billion synaptic events/s when simulated with a 1 ms time step. Its low baseline power of less than 250 mW allows for efficiency even under varying workload conditions, allowing to explore sparse and event-based modes of computation. All this demonstrates the chip's capabilities as a universal hardware platform for scalable brain-inspired computing and its combinations with mainstream deep network approaches.

Problem

• neuromorphic computing
• deep learning
• energy efficiency
• scalable hardware
• brain-inspired computing

Innovation

• neuromorphic computing
• spiking neural networks
• event-based communication
• energy efficiency
• many-core architecture