Approximate Logic Synthesis Using BLASYS

2025-06-28

AI Summary

This work addresses the fundamental trade-off between accuracy and hardware cost in approximate computing. We propose a tunable-accuracy approximate logic synthesis methodology based on Boolean Matrix Factorization (BMF). By modeling circuit truth tables as Boolean matrices, BMF enables controllable accuracy approximation; integrated with subcircuit partitioning, optimization-aware ordering, and systematic design-space exploration, the approach ensures scalability to large-scale circuits. Implemented end-to-end within an open-source EDA flow, our method achieves, on average, a 48.14% reduction in area overhead and only a 5% mean relative error across multiple benchmark circuits—significantly improving energy efficiency and resource utilization. The key contributions are: (i) the first systematic application of BMF to approximate logic synthesis, and (ii) a novel synthesis framework enabling smooth, fine-grained trade-offs between accuracy and area.

Technology Category

• Machine Learning: Hardware-aware ML
• Knowledge Representation and Reasoning: Computational Complexity of Reasoning
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories

Application Category

• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Security and Privacy: Large-scale security measurements

Abstract

Approximate computing is an emerging paradigm where design accuracy can be traded for improvements in design metrics such as design area and power consumption. In this work, we overview our open-source tool, BLASYS, for synthesis of approximate circuits using Boolean Matrix Factorization (BMF). In our methodology the truth table of a given circuit is approximated using BMF to a controllable approximation degree, and the results of the factorization are used to synthesize the approximate circuit output. BLASYS scales up the computations to large circuits through the use of partition techniques, where an input circuit is partitioned into a number of interconnected subcircuits and then a design-space exploration technique identifies the best order for subcircuit approximations. BLASYS leads to a graceful trade-off between accuracy and full circuit complexity as measured by design area. Using an open-source design flow, we extensively evaluate our methodology on a number of benchmarks, where we demonstrate that the proposed methodology can achieve on average 48.14% in area savings, while introducing an average relative error of 5%.

Problem

• Develops BLASYS for approximate circuit synthesis
• Balances accuracy and design complexity trade-offs
• Achieves significant area savings with minimal error

Innovation

• Uses Boolean Matrix Factorization for approximation
• Scales via partition and exploration techniques
• Achieves area savings with controlled error