SMT-Sweep: Word-Level Representation Unification for Hardware Verification

2025-07-01

AI Summary

In hardware verification, existing SAT-based sweeping techniques operate exclusively at the bit-level, rendering them inefficient for word-level constructs such as bit-vector operations and arrays. To address this limitation, we propose SMT-Sweep—the first SMT-extended sweeping framework designed specifically for word-level hardware verification. Our approach elevates sweeping to the word-level semantic domain by unifying structural hashing, random word-level simulation, and constraint-driven symbolic solving to model and simplify circuits containing bit-vectors and arrays. Crucially, simulation-assisted equivalence checking enables high-fidelity logic compression. Experimental evaluation demonstrates that SMT-Sweep achieves 44× and 69× speedups over state-of-the-art bit-level SAT sweeping and pure word-level SMT solvers, respectively. This marks a significant advancement in the practicality and scalability of word-level formal verification.

Technology Category

• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories
• Machine Learning: Hardware-aware ML
• Search and Optimization: Sampling/Simulation-based Search

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics
• Web Mining and Content Analysis: Web data generation and simulation

Abstract

SAT sweeping has long been a cornerstone technique in logic simplification and equivalence checking at the bit level, leveraging structural hashing, simulation and SAT solving to prune redundant logic. However, with the growing adoption of word-level constructs in hardware verification, such as bit-vector operations, arithmetics and arrays, there lacks a counterpart of SAT sweeping at the word level. In this paper, we introduce SMT-Sweep, a novel extension of SAT sweeping into the word level, grounded in Satisfiability Modulo Theories (SMT). SMT-Sweep takes advantage of simulation and equivalence detection to handle SMT terms with rich bit-vector operations and array semantics. Our framework incorporates both randomized and constraint-driven word-level simulation tailored to symbolic expressions and operator semantics beyond pure Boolean logic. Experimental results show that SMT-Sweep achieves significant speed-up compared to state-of-the-art bit-level SAT sweeping and word-level monolithic SMT solving (averaging around 44x and 69x, respectively).To the best of our knowledge, this is the first work that brings sweeping techniques to SMT-based hardware verification. The implementation is open-sourced at: https://github.com/yangziyiiii/SMT-Sweep.

Problem

• Extends SAT sweeping to word-level hardware verification
• Handles SMT terms with bit-vector and array operations
• Improves speed over bit-level SAT and monolithic SMT

Innovation

• Extends SAT sweeping to word-level using SMT
• Uses simulation and equivalence for SMT terms
• Incorporates randomized and constraint-driven simulation