🤖 AI Summary
Heterogeneous FPGAs—integrating DSPs, memory blocks, and domain-specific accelerators—improve PPA but exacerbate design-space exploration complexity due to tight resource coupling. To address this, we propose a lightweight consistency-aware analysis method inspired by the Roofline model, enabling early-stage co-optimization across heterogeneous resources. We introduce three novel consistency metrics to rapidly identify utilization bottlenecks in critical resources such as DSPs and memories. Evaluated on the Stratix 10 FPGA using Koios and VPR benchmarks, our approach performs low-overhead performance profiling. It significantly reduces architectural exploration complexity while preserving modeling efficiency, thereby effectively supporting architecture-application co-optimization for emerging workloads—including machine learning—without sacrificing prediction accuracy or design productivity.
📝 Abstract
Field-Programmable Gate Arrays (FPGAs) have evolved from uniform logic arrays into heterogeneous fabrics integrating digital signal processors (DSPs), memories, and specialized accelerators to support emerging workloads such as machine learning. While these enhancements improve power, performance, and area (PPA), they complicate design space exploration and application optimization due to complex resource interactions.
To address these challenges, we propose a lightweight profiling methodology inspired by the Roofline model. It introduces three congruence scores that quickly identify bottlenecks related to heterogeneous resources, fabric, and application logic. Evaluated on the Koios and VPR benchmark suites using a Stratix 10 like FPGA, this approach enables efficient FPGA architecture co-design to improve heterogeneous FPGA performance.