Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper

2025-07-14

AI Summary

To address low LUT mapping accuracy and insufficient delay–area optimization in FPGA logic synthesis, this paper proposes FuseMap: a novel framework that jointly models ASIC standard-cell mapping and FPGA LUT mapping for the first time, enabling an incremental co-optimization architecture. It incorporates reinforcement learning to dynamically select logic units and determine mapping strategies, achieving design-specific optimization. FuseMap further supports joint tuning across multiple technology libraries and mainstream mapping tools. Experimental evaluation on ISCAS, ITC, VTR, and EPFL benchmark circuits demonstrates that, compared to state-of-the-art methods, FuseMap reduces critical-path delay by 12.3% on average, decreases logic area by 9.7%, and improves mapping accuracy—evidenced by an 8.5% increase in LUT coverage—thereby significantly enhancing overall FPGA synthesis quality.

Technology Category

• Search and Optimization: Learning to Search
• Computer Vision: Learning & Optimization for CV
• Natural Language Processing: Learning & Optimization for NLP

Application Category

• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking

Abstract

LUT (Look-Up Table) mapping is a critical step in FPGA logic synthesis, where a logic network is transformed into a form that can be directly implemented using the FPGA's LUTs. An FPGA LUT is a flexible digital memory structure that can implement any logic function of a limited number of inputs, typically 4 to 6 inputs, depending on the FPGA architecture. The goal of LUT mapping is to map the Boolean network into LUTs, where each LUT can implement any function with a fixed number of inputs. In parallel to FPGA technology mapping, ASIC technology mapping maps the Boolean network to user-defined standard cells, which has traditionally been developed separately from LUT mapping algorithms. However, in this work, our motivating examples demonstrate that ASIC technology mappers can potentially improve the performance of LUT mappers, such that standard cell mapping and LUT mapping work in an incremental manner. Therefore, we propose the FuseMap framework, which explores this opportunity to improve LUT mapping in the FPGA design flow by utilizing reinforcement learning to make design-specific choices during cell selection. The effectiveness of FuseMap is evaluated on a wide range of benchmarks, different technology libraries, and technology mappers. The experimental results demonstrate that FuseMap achieves higher mapping accuracy while reducing delay and area across diverse circuit designs collected from ISCAS 85/89, ITC/ISCAS 99, VTR 8.0, and EPFL benchmarks.

Problem

• Improving FPGA LUT mapping using ASIC mapper techniques
• Enhancing LUT mapping performance via reinforcement learning
• Reducing delay and area in FPGA design flow

Innovation

• Combines ASIC and FPGA mapping techniques
• Uses reinforcement learning for cell selection
• Improves mapping accuracy, reduces delay and area