AssertFix: Empowering Automated Assertion Fix via Large Language Models

2025-09-28

AI Summary

SystemVerilog assertions in RTL verification are error-prone and difficult to maintain, while existing automated assertion generation methods lack repair capabilities. Method: This paper proposes AssertFix—the first end-to-end, LLM-based assertion auto-repair framework—integrating RTL semantic understanding, precise error localization, root-cause diagnosis, and fine-grained error classification, enabling customizable repair strategies and minimizing manual intervention. Unlike conventional approaches that treat assertion generation as a post-verification task, AssertFix achieves full automation from error identification to correction. Contribution/Results: Evaluated on the OpenCores benchmark, AssertFix improves assertion repair rate by 42.6% and increases verification coverage by 18.3% on average, demonstrating its effectiveness, robustness, and practical engineering applicability.

Technology Category

Planning, Routing, and Scheduling: Replanning and Plan RepairKnowledge Representation and Reasoning: Automated Reasoning and Theorem ProvingMachine Learning: Calibration & Uncertainty Quantification

Application Category

Search and Retrieval-Augmented AI: Web evaluation methodologies and metricsSemantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMsEconomics, Online Markets and Human Computation: Cost models of using LLMs in production systems

Abstract

Assertion-based verification (ABV) is critical in ensuring that register-transfer level (RTL) designs conform to their functional specifications. SystemVerilog Assertions (SVA) effectively specify design properties, but writing and maintaining them manually is challenging and error-prone. Although recent progress of assertion generation methods leveraging large language models (LLMs) have shown great potential in improving assertion quality, they typically treat assertion generation as a final step, leaving the burden of fixing of the incorrect assertions to human effects, which may significantly limits the application of these methods. To address the above limitation, we propose an automatic assertion fix framework based on LLMs, named AssertFix. AsserFix accurately locates the RTL code related to the incorrect assertion, systematically identifies the root causes of the assertion errors, classifies the error type and finally applies dedicated fix strategies to automatically correct these errors, improving the overall quality of the generated assertions. Experimental results show that AssertFix achieves noticeable improvements in both fix rate and verification coverage across the Opencore benchmarks.

Problem

• Automatically fixing incorrect SystemVerilog Assertions in RTL verification
• Addressing manual assertion maintenance challenges through LLM-based solutions
• Improving assertion quality by identifying root causes and applying fixes

Innovation

• Automatically fixes incorrect assertions using LLMs
• Locates RTL code and identifies assertion error causes
• Applies dedicated strategies to improve verification coverage