AssertGen: Enhancement of LLM-aided Assertion Generation through Cross-Layer Signal Bridging

2025-09-28

AI Summary

Existing LLM-based assertion generation methods struggle to model cross-layer semantic correlations between design specifications and RTL code, resulting in low assertion coverage and poor accuracy. To address this, we propose a cross-layer signal bridging mechanism that integrates chain-of-thought reasoning with signal mapping analysis to explicitly align natural-language specifications with RTL signal semantics, enabling precise, automated SystemVerilog assertion generation. Our end-to-end framework synergistically combines large language models, formal verification, and mutation testing feedback to significantly enhance assertion completeness and verifiability. Experimental evaluation demonstrates that our approach outperforms state-of-the-art methods across key metrics—including formal verification pass rate, cone-of-influence coverage, proof-core coverage, and mutation kill rate—establishing new performance benchmarks for specification-driven assertion synthesis.

Technology Category

Natural Language Processing: Code Generation / Program Synthesis from Natural LanguageKnowledge Representation and Reasoning: Automated Reasoning and Theorem ProvingMachine Learning: Large Multimodal Models (LMMs)

Application Category

Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMsSearch and Retrieval-Augmented AI: Multilingual and cross-lingual Web searchEconomics, Online Markets and Human Computation: Cost models of using LLMs in production systems

Abstract

Assertion-based verification (ABV) serves as a crucial technique for ensuring that register-transfer level (RTL) designs adhere to their specifications. While Large Language Model (LLM) aided assertion generation approaches have recently achieved remarkable progress, existing methods are still unable to effectively identify the relationship between design specifications and RTL designs, which leads to the insufficiency of the generated assertions. To address this issue, we propose AssertGen, an assertion generation framework that automatically generates SystemVerilog assertions (SVA). AssertGen first extracts verification objectives from specifications using a chain-of-thought (CoT) reasoning strategy, then bridges corresponding signals between these objectives and the RTL code to construct a cross-layer signal chain, and finally generates SVAs based on the LLM. Experimental results demonstrate that AssertGen outperforms the existing state-of-the-art methods across several key metrics, such as pass rate of formal property verification (FPV), cone of influence (COI), proof core and mutation testing coverage.

Problem

• Bridging specification-RTL design relationship gaps
• Enhancing LLM-generated assertion quality
• Automating SystemVerilog assertion generation process

Innovation

• Uses chain-of-thought reasoning to extract objectives
• Bridges signals between specifications and RTL code
• Generates assertions based on cross-layer signal chains