GAP-LA: GPU-Accelerated Performance-Driven Layer Assignment

2025-07-12

AI Summary

In VLSI global routing, layer assignment—allocating metal layers to 2D routing paths in 3D space—must jointly optimize timing, power, and congestion, yet efficient multi-objective optimization remains highly challenging. This paper proposes the first performance-driven, GPU-accelerated layer assignment framework that unifies timing, power, and congestion into a single, co-optimized objective. Leveraging customized parallel algorithms and memory-access optimizations, our framework scales to ultra-large designs with up to 12 million nets. Evaluated against the ISPD 2025 winning solution, it achieves 0.3%–9.9% improvement in worst negative slack (WNS) and 2.0%–5.4% reduction in total negative slack (TNS), while simultaneously constraining power consumption and routing congestion. These results significantly outperform existing single- or dual-objective approaches, demonstrating superior scalability and Pareto-optimal trade-off management across all three critical metrics.

Technology Category

• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization
• Search and Optimization: Combinatorial Optimization

Application Category

• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines

Abstract

Layer assignment is critical for global routing of VLSI circuits. It converts 2D routing paths into 3D routing solutions by determining the proper metal layer for each routing segments to minimize congestion and via count. As different layers have different unit resistance and capacitance, layer assignment also has significant impacts to timing and power. With growing design complexity, it becomes increasingly challenging to simultaneously optimize timing, power, and congestion efficiently. Existing studies are mostly limited to a subset of objectives. In this paper, we propose a GPU-accelerated performance-driven layer assignment framework, GAP-LA, for holistic optimization the aforementioned objectives. Experimental results demonstrate that we can achieve 0.3%-9.9% better worst negative slack (WNS) and 2.0%-5.4% better total negative slack (TNS) while maintaining power and congestion with competitive runtime compared with ISPD 2025 contest winners, especially on designs with up to 12 millions of nets.

Problem

• Optimizes timing, power, and congestion in VLSI routing
• Converts 2D paths to 3D solutions via layer assignment
• GPU-accelerated holistic optimization for large-scale designs

Innovation

• GPU-accelerated layer assignment framework
• Holistic optimization of timing, power, congestion
• Performance-driven routing for VLSI circuits