🤖 AI Summary
This study addresses the problem of reliably observing causal order in shared-memory concurrent systems (COP), formalizing its observability limits and proving that strong consistency—defined as both completeness and reliability—is generally unattainable. The key insight is that the placement of monitoring instrumentation, rather than the choice of timestamp mechanism, fundamentally determines observability guarantees. To this end, the work proposes three non-blocking monitor implementations: FAInc (a centralized atomic counter), Striped (a decentralized counter), and Collect (an iterative register snapshot). Theoretically, all three provide equivalent COP guarantees. Experimental evaluation on a 64-core NUMA architecture demonstrates that Striped achieves throughput comparable to Collect while maintaining linearizability and substantially alleviating the cache contention bottleneck inherent in FAInc.
📝 Abstract
Determining whether one concurrent operation completed before another began is a fundamental prerequisite for reasoning about the correctness of concurrent systems. We formalize this challenge as the Causal Observability Problem (COP): assign timestamps to the observable boundary events of a concurrent execution, invocations and responses, that faithfully reflect real-time operation order. A solution is complete if it never misses a genuine precedence, and sound if it never reports a spurious one. We prove that a strongly consistent solution, one that is simultaneously complete and sound, is unachievable at the observable boundary. We then show that the placement of instrumentation events relative to operation boundaries deterministically governs what a monitor can guarantee: internal placement yields completeness, external placement yields soundness, and neither achieves both. This dichotomy holds independently of the underlying timestamp mechanism. We instantiate this framework with three non-blocking implementations of a Causal Monitor object: FAInc (centralized atomic counter), Striped (decentralized counter), and Collect (iterative register snapshot). FAInc and Striped are linearizable; Collect is only quiescently consistent. Despite this internal consistency gap, we prove that all three provide identical COP guarantees: placement alone determines observable behavior. We validate these claims empirically on a 64-core NUMA architecture, showing that Striped matches Collect in throughput while preserving linearizability, resolving the cache-contention bottleneck of FAInc at high thread counts.