Technology Category
Machine Learning: Hardware-aware MLPlanning, Routing, and Scheduling: Optimization of Spatio-temporal SystemsSearch and Optimization: Distributed Search
Enabling Time-Aware Priority Traffic Management over Distributed FPGA Nodes
🤖 AI Summary
To address the challenges of bandwidth guarantee and low scheduling precision for multi-service traffic in distributed FPGA nodes, this paper proposes a time-aware, NIC-level priority traffic management mechanism. Based on the open-source Corundum NIC framework, we design and implement an FPGA-based hardware scheduler supporting time-slice allocation, exposing programmable registers via the AXI bus to enable dynamic, fine-grained bandwidth configuration of priority queues at the driver layer. Concurrently, we integrate Linux QDISC for traffic classification and host-side cooperative scheduling. This approach synergistically combines hardware-level deterministic scheduling with software-level controllability, achieving low-overhead, highly reliable time-aware traffic control on heterogeneous FPGA-NIC architectures. Experimental results demonstrate precise bandwidth allocation across priority levels, significantly improving transmission performance and flow isolation for high-priority services.
Technology Category
Application Category
📝 Abstract
Network Interface Cards (NICs) greatly evolved from simple basic devices moving traffic in and out of the network to complex heterogeneous systems offloading host CPUs from performing complex tasks on in-transit packets. These latter comprise different types of devices, ranging from NICs accelerating fixed specific functions (e.g., on-the-fly data compression/decompression, checksum computation, data encryption, etc.) to complex Systems-on-Chip (SoC) equipped with both general purpose processors and specialized engines (Smart-NICs). Similarly, Field Programmable Gate Arrays (FPGAs) moved from pure reprogrammable devices to modern heterogeneous systems comprising general-purpose processors, real-time cores and even AI-oriented engines. Furthermore, the availability of high-speed network interfaces (e.g., SFPs) makes modern FPGAs a good choice for implementing Smart-NICs. In this work, we extended the functionalities offered by an open-source NIC implementation (Corundum) by enabling time-aware traffic management in hardware, and using this feature to control the bandwidth associated with different traffic classes. By exposing dedicated control registers on the AXI bus, the driver of the NIC can easily configure the transmission bandwidth of different prioritized queues. Basically, each control register is associated with a specific transmission queue (Corundum can expose up to thousands of transmission and receiving queues), and sets up the fraction of time in a transmission window which the queue is supposed to get access the output port and transmit the packets. Queues are then prioritized and associated to different traffic classes through the Linux QDISC mechanism. Experimental evaluation demonstrates that the approach allows to properly manage the bandwidth reserved to the different transmission flows.
Problem
Research questions and friction points this paper is trying to address.
Enabling time-aware traffic management on FPGA-based NICs
Controlling bandwidth allocation for different traffic classes
Configuring prioritized transmission queues through hardware registers
Innovation
Methods, ideas, or system contributions that make the work stand out.
Extended open-source NIC with time-aware traffic management
Used control registers to configure queue transmission bandwidth
Integrated hardware scheduling with Linux QDISC prioritization
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