Optimizing Tree-structure Indexes for CXL-based Heterogeneous Memory with SINLK

2025-07-24

AI Summary

In CXL-based heterogeneous memory (CXL-HM), tree indexes (e.g., B⁺-trees, radix trees) suffer from suboptimal performance due to coarse-grained, page-level data placement misaligned with fine-grained tree node access patterns. To address this, we propose SINLK—the first CXL-native, tree-structure-aware, node-level fine-grained data layout framework. SINLK bridges the semantic gap between hardware capabilities and data structure semantics by co-optimizing node-level placement decisions with CXL memory’s bandwidth, latency, and persistence characteristics. It requires no modifications to existing index logic, enabling seamless migration of legacy tree structures. Evaluated under YCSB and real-world workloads, SINLK achieves up to 71% higher throughput and reduces P99 latency by 81% compared to state-of-the-art approaches such as MEMTIS.

Technology Category

• Search and Optimization: Distributed Search
• Machine Learning: Hardware-aware ML
• Data Mining & Knowledge Management: Scalability, Parallel & Distributed Systems

Application Category

• Graph Algorithms and Modeling for the Web: Querying, indexing, and retrieval in Web-related graphs
• Search and Retrieval-Augmented AI: Web crawling and indexing
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems

Abstract

On heterogeneous memory (HM) where fast memory (i.e., CPU-attached DRAM) and slow memory (e.g., remote NUMA memory, RDMA-connected memory, Persistent Memory (PM)) coexist, optimizing the placement of tree-structure indexes (e.g., B+tree) is crucial to achieving high performance while enjoying memory expansion. Nowadays, CXL-based heterogeneous memory (CXL-HM) is emerging due to its high efficiency and memory semantics. Prior tree-structure index placement schemes for HM cannot effectively boost performance on CXL-HM, as they fail to adapt to the changes in hardware characteristics and semantics. Additionally, existing CXL-HM page-level data placement schemes are not efficient for tree-structure indexes due to the granularity mismatch between the tree nodes and the page. In this paper, we argue for a CXL native, tree-structure aware data placement scheme to optimize tree-structure indexes on CXL-HM. Our key insight is that the placement of tree-structure indexes on CXL-HM should match the tree's inherent characteristics with CXL-HM features. We present SINLK, a tree-structure aware, node-grained data placement scheme for tree-structure indexes on CXL-HM. With SINLK, developers can easily adapt existing tree-structure indexes to CXL-HM. We have integrated the B+tree and radix tree with SINLK to demonstrate its effectiveness. Evaluations show that SINLK improves throughput by up to 71% and reduces P99 latency by up to 81% compared with state-of-the-art data placement schemes (e.g., MEMTIS) and HM-optimized tree-structure indexes in YCSB and real-world workloads.

Problem

• Optimizing tree-structure indexes for CXL-based heterogeneous memory
• Addressing granularity mismatch in tree nodes and memory pages
• Improving performance and latency in CXL-HM data placement

Innovation

• CXL native tree-structure aware placement
• Node-grained data placement scheme
• Adapts existing indexes to CXL-HM