Towards System-Level Quantum-Accelerator Integration

2025-07-25

AI Summary

Quantum-classical system-level integration faces challenges including high latency, weak determinism, and architectural heterogeneity. Method: This paper proposes a vertically integrated quantum-classical co-architecture: it abstracts the quantum processor as a schedulable peripheral device and designs a kernel-level Quantum Abstraction Layer (QAL) to enable low-latency, high-throughput real-time coordination and unified cross-architecture resource management. It innovatively supports tightly coupled tasks such as quantum error correction and implements a multi-architecture (x86_64/ARM64/RISC-V) quantum virtualization framework built upon QEMU, augmented with FPGA-based cycle-accurate timing simulation for full-system validation. Contribution/Results: Experiments demonstrate functional completeness and scalable performance across all three architectures. The work delivers the first extensible architecture blueprint supporting kernel-level quantum scheduling and hardware-software co-design, accompanied by an open-source simulation infrastructure for quantum-classical hybrid computing.

Technology Category

• Machine Learning: Quantum Machine Learning
• Cognitive Modeling & Cognitive Systems: Agent Architectures
• Knowledge Representation and Reasoning: Qualitative Reasoning

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Virtualization and resource management in Web systems and infrastructures
• Economics, Online Markets and Human Computation: Architectures and workflows that use LLMs for crowd work
• Search and Retrieval-Augmented AI: Vertical and domain-specific search

Abstract

Quantum computers are often treated as experimental add-ons that are loosely coupled to classical infrastructure through high-level interpreted languages and cloud-like orchestration. However, future deployments in both, high-performance computing (HPC) and embedded environments, will demand tighter integration for lower latencies, stronger determinism, and architectural consistency, as well as to implement error correction and other tasks that require tight quantum-classical interaction as generically as possible. We propose a vertically integrated quantum systems architecture that treats quantum accelerators and processing units as peripheral system components. A central element is the Quantum Abstraction Layer (QAL) at operating system kernel level. It aims at real-time, low-latency, and high-throughput interaction between quantum and classical resources, as well as robust low-level quantum operations scheduling and generic resource management. It can serve as blueprint for orchestration of low-level computational components "around" a QPU (and inside a quantum computer), and across different modalities. We present first results towards such an integrated architecture, including a virtual QPU model based on QEMU. The architecture is validated through functional emulation on three base architectures (x86_64, ARM64, and RISC-V), and timing-accurate FPGA-based simulations. This allows for a realistic evaluation of hybrid system performance and quantum advantage scenarios. Our work lays the ground for a system-level co-design methodology tailored for the next generation of quantum-classical computing.

Problem

• Tighter integration of quantum and classical computing systems
• Low-latency high-throughput quantum-classical interaction
• System-level co-design for quantum-classical computing

Innovation

• Vertically integrated quantum systems architecture
• Quantum Abstraction Layer at kernel level
• Virtual QPU model with QEMU emulation