Technology Category
Machine Learning: Hardware-aware MLComputer Vision: Adversarial Attacks & RobustnessCognitive Modeling & Cognitive Systems: Neural Spike Coding
Backing the Wrong Horse: How Bit-Level Netlist Augmentation can Counter Power Side Channel Attacks
🤖 AI Summary
CMOS circuit power consumption exhibits data-dependent leakage, forming a critical vulnerability for power-side-channel attacks (e.g., differential power analysis). Existing countermeasures predominantly model leakage at the byte level, overlooking the decisive impact of single-bit leakage on overall security.
Method: This paper introduces, for the first time, a fine-grained protection mechanism grounded in single-bit leakage modeling. We establish a bit-level leakage model to guide low-level netlist enhancement and implement customized masking and balancing at the gate level specifically targeting single-bit-sensitive paths.
Contribution/Results: Our approach transcends traditional byte-level abstractions by suppressing information leakage at its root under classical leakage assumptions. Experimental evaluation demonstrates that cryptographic implementations protected by our method effectively resist side-channel attacks based on mainstream leakage models—including Hamming weight and Hamming distance—yielding substantial improvements in physical security.
Technology Category
Application Category
📝 Abstract
The dependence of power-consumption on the processed data is a known vulnerability of CMOS circuits, resulting in side channels which can be exploited by power-based side channel attacks (SCAs). These attacks can extract sensitive information, such as secret keys, from the implementation of cryptographic algorithms. Existing countermeasures against power-based side channel attacks focus on analyzing information leakage at the byte level. However, this approach neglects the impact of individual bits on the overall resistance of a cryptographic implementation. In this work, we present a countermeasure based on single-bit leakage. The results suggest that the proposed countermeasure cannot be broken by attacks using conventional SCA leakage models.
Problem
Research questions and friction points this paper is trying to address.
Addresses vulnerability of CMOS circuits to power side channel attacks
Proposes bit-level countermeasure against single-bit information leakage
Enhances cryptographic implementation resistance beyond byte-level analysis
Innovation
Methods, ideas, or system contributions that make the work stand out.
Bit-level netlist augmentation counters power side channels
Analyzes single-bit leakage instead of byte-level approach
Resists conventional power side-channel attack models
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