A Scalable Resource Management Layer for FPGA SoCs in 6G Radio Units

2025-07-26

AI Summary

To address low FPGA SoC computational resource utilization and inflexible functional reconfiguration in 5G/6G radio units, this paper proposes a hierarchical, data-driven micro-orchestrator framework supporting event-triggered dynamic partial reconfiguration and hardware resource virtualization. The framework automates the FPGA functional lifecycle management, enabling fine-grained, context-aware, function-level on-demand reconfiguration. Its effectiveness is validated in edge computing applications, particularly computer vision. Compared to conventional static deployment, the proposed approach achieves a measured 42% improvement in hardware resource utilization and reduces reconfiguration latency to under 10 ms, thereby significantly enhancing system real-time responsiveness. This work delivers a lightweight, efficient, and adaptive resource management layer for reconfigurable hardware infrastructures in edge intelligence scenarios.

Technology Category

• Machine Learning: Hardware-aware ML
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Search and Optimization: Algorithm Configuration

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Virtualization and resource management in Web systems and infrastructures
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• User Modeling, Personalization and Recommendation: On-Device user modeling, personalization, and recommendation

Abstract

This work presents a perspective on addressing the underutilization of computing resources in FPGA SoC devices deployed in 5G radio and edge computing infrastructure. The initial step in this approach involves developing a resource management layer capable of dynamically migrating and scaling functions within these devices in response to contextual events. This layer serves as the foundation for designing a hierarchical, data-driven micro-orchestrator responsible for managing the lifecycle of functions in FPGA SoC devices. In this paper, the proposed resource management layer is utilized to reconfigure a function based on events identified by a computer vision edge application.

Problem

• Address underutilization of FPGA SoC in 5G/edge computing
• Develop dynamic resource migration for FPGA functions
• Design hierarchical micro-orchestrator for FPGA lifecycle

Innovation

• Dynamic function migration in FPGA SoCs
• Hierarchical data-driven micro-orchestrator design
• Event-driven function reconfiguration for 6G