A Low-Latency ASIC Architecture for Real-Time Line Segment Detection

2026-08-06

AI Summary

This work addresses the challenge of achieving real-time performance, low power consumption, and deterministic latency in line detection for resource-constrained embedded vision systems. The authors propose a fully pipelined ASIC architecture based on a stepping algorithm that enables deterministic, low-latency processing of one pixel per clock cycle. Key innovations include five ASIC-specific optimizations: register-level line buffering with data reuse, multiplier-free MCM filtering, 8-direction angle quantization, CAM-based single-cycle matching, and an efficient duplicate-removal mechanism. Implemented in 45 nm CMOS technology, the design achieves 325 FPS at VGA resolution (406 FPS at 125 MHz) and 48 FPS at Full HD, with only 25.54 mW power consumption and a core area of 0.412 mm². Compared to a 90 nm Hough transform-based implementation, it reduces power by 49% and increases frame rate by over 1.6×.

Abstract

Line segment detection is a critical preprocessing step in embedded vision applications such as autonomous navigation, visual SLAM, and industrial inspection. Deep learning methods achieve high accuracy but require substantial resources, limiting their deployment on resource-constrained platforms. Classical algorithms are efficient but exhibit content-dependent latency. This paper presents a low-latency ASIC architecture for real-time line segment detection. The proposed design is based on the step-length algorithm and incorporates five ASIC-specific features: register-based line buffering with data reuse, multiplierless MCM-based filtering, 8-class angle quantization, a CAM-like associative memory for single-cycle matching, and an optimized duplicate removal mechanism. The architecture is fully pipelined and processes one pixel per clock cycle with deterministic latency. Synthesized in a 45nm CMOS process, the design achieves 325 FPS at VGA resolution and 48 FPS at Full HD, with 25.54 mW power consumption and 0.412 mm\textsuperscript{2} area. At 125 MHz, the throughput increases to 406 FPS at VGA resolution with 31.48 mW power consumption. Compared with a 90nm ASIC implementation based on the Line Hough Transform, the proposed design reduces power consumption by 49\% and delivers over 1.6 times higher frame rate. The architecture is well suited for edge-computing applications requiring real-time performance, low power, and minimal area.

Problem

• line segment detection
• low-latency
• ASIC architecture
• real-time
• embedded vision

Innovation

• low-latency ASIC
• line segment detection
• real-time vision
• edge computing
• pipelined architecture