Retention-Aware RISC-V ISA Extension and Memory Controller on FPGA for MLC NVM

2026-08-06

AI Summary

This work addresses the inherent trade-off between write speed and data retention in multi-level cell non-volatile memory (MLC NVM), a challenge exacerbated by the absence of hardware-level co-optimization mechanisms in existing systems. To tackle this, the authors propose a retention-aware RISC-V instruction set extension coupled with a bit-significance-aware AXI slave peripheral, along with a finite state machine–based efficient burst transfer controller. Implemented on FPGA, this approach enables synergistic optimization of performance and reliability for MLC NVM write operations. Experimental results demonstrate minimal hardware overhead—less than 0.08%—while the new fast-store instructions improve streaming workload performance by over 7%. The bit-level AXI peripheral consumes fewer than 3.5% of LUTs for a 64×64 matrix and reduces controller resource usage by 30%.

Abstract

Non-volatile memory (NVM) technologies, particularly Multi-Level Cell (MLC) NVMs, offer significant potential for increasing memory density. MLC NVMs provide a tradeoff between write latency and retention time, where faster writes/stores result in lower retention and slower writes yield higher retention. However, limited work has been done to validate and prototype NVM-based systems in hardware, leveraging this tradeoff at the system level. In this paper, we present a novel memory controller architecture and a RISC-V instruction set extension to optimize MLC NVM write operations by balancing speed and retention time. Our custom NVM controller, built around a finite state machine with an AXI memory-mapped interface, efficiently manages read/write operations with enhanced burst transfers, minimizing latency. Additionally, we introduce a fast-store instruction in RISC-V to increasing write performance while addressing retention limitations. Further, we design a dedicated AXI slave peripheral that supports bit-significance-aware writes: critical bits (e.g., MSBs) are written using slower, high-retention writes, while non-critical bits (e.g., LSBs) use faster, low-retention writes to help enhance performance without compromising data reliability. These enhancements are implemented in hardware on an FPGA platform. Experimental results show that our controller reduces hardware overhead by 30% compared to conventional designs, and the fast-store instruction improves performance by over 7% for streaming workloads with less than 0.08% hardware overhead. The bit-wise AXI peripheral has a LUT utilization staying below 3.5% even for 64x64 matrices, and under 1% for 32x32 sizes, making it viable for integration into larger SoCs.

Problem

• MLC NVM
• retention time
• write latency
• RISC-V ISA extension
• memory controller

Innovation

• RISC-V ISA extension
• MLC NVM
• Retention-aware write
• Bit-significance-aware memory controller
• FPGA prototype