Ising Acceleration for Multi-Robot Multi-Target Planning

2026-08-07

AI Summary

This work addresses the combinatorial optimization challenge in multi-robot, multi-target planning by proposing an efficient solution tailored for low-power CMOS Ising hardware. The approach recursively decomposes the problem into three layers—target assignment, path construction, and routing—and maps them onto a fully connected Ising chip with only 45 spins and limited precision through a multi-stage pipeline involving spin merging, coefficient quantization, and a spin budget branching strategy. Experimental results demonstrate that the proposed recursive target assignment mechanism reduces energy consumption by a factor of 8,000 compared to classical baselines, while maintaining end-to-end planning performance within 9% of optimal. Overall, the method achieves a 130× reduction in total energy usage, substantially enhancing optimization efficiency and scalability for energy-constrained robotic systems.

Abstract

Ising machines are emerging as promising hardware for combinatorial optimization. With recent advances in CMOS Ising technology, they are becoming attractive as low-power accelerator systems for robotics, where energy is limited and combinatorial optimization arises in multiple forms. However, a hardware-aware analysis of where such chips fit within a robotics planning stack is still missing. This paper studies the capabilities and limitations of CMOS Ising machines for low-power acceleration in multi-robot multi-target planning. We analyze three planning layers---target sharing, tour construction, and pathfinding---using real 45-spin all-to-all connected CMOS Ising chips as representative devices. We propose new Ising-based planning methods and a multi-mapping pipeline that uses spin merging, coefficient quantization, and spin-budget branching to adapt subproblems to spin- and coefficient-limited hardware. Our results show that the proposed recursive target-sharing method naturally matches the Ising hardware, achieving up to 8,000x lower energy than a classical baseline. End to end, the Ising pipeline produces routes within 9% of a strong classical baseline at 130x lower energy, showing that compact CMOS Ising machines can be effective in selected parts of the planning stack.

Problem

• Ising machines
• multi-robot planning
• combinatorial optimization
• low-power acceleration
• CMOS hardware

Innovation

• Ising machine
• CMOS accelerator
• multi-robot planning
• combinatorial optimization
• hardware-aware mapping