Circuit-Based Program Verification: Sequential Circuits as an Intermediate Representation for Verifying C Programs

2026-08-07

AI Summary

This work addresses the longstanding divide between software and hardware verification, which has been hindered by the absence of a common intermediate representation that would enable direct application of efficient hardware model checking techniques to C programs. To bridge this gap, the paper introduces the Circuit-based Program Verification (CPV) framework, which systematically compiles C programs into sequential circuits, unifying control-flow and data-flow semantics within a single formal model. CPV integrates established hardware model checking algorithms—including Bounded Model Checking (BMC), k-induction, and IC3/PDR—to support both reachability safety and termination verification. Moreover, it automatically translates counterexamples back into human-readable software evidence. Evaluated on a benchmark suite of over 16,000 verification tasks, CPV matches the performance of leading software verifiers and successfully solves instances beyond the reach of existing tools, demonstrating significant complementary strengths.

Abstract

Formal verification of software programs and hardware designs shares the common goal of reasoning about state-transition systems, yet the two communities have largely developed separate intermediate representations and verification algorithms. This paper investigates sequential circuits as an intermediate representation for software verification, with the goal of enabling direct application of hardware-model-checking techniques. We present Circuit-Based Program Verification (CPV), a modular framework that translates C programs into sequential circuits and employs off-the-shelf hardware model checkers as backends. Unlike traditional software verifiers, which typically rely on path-based exploration, CPV reasons over sequential circuits, where a program's control and data flows are folded into a monolithic transition relation that can be analyzed as a whole. The framework supports reachability-safety and termination analyses and integrates multiple state-of-the-art hardware model checkers, which together provide access to diverse verification algorithms, including bounded model checking, $k$-induction, and IC3/PDR. Counterexamples found by hardware model checkers are automatically translated back into software-verification witnesses for users to interpret verification results. We conducted a comprehensive evaluation on a benchmark suite of more than 16000 tasks. Our results show that CPV achieved competitive performance against five well-established software verifiers and exhibited complementary strengths by uniquely solving tasks that other verifiers cannot handle.

Problem

• software verification
• hardware model checking
• sequential circuits
• intermediate representation
• formal verification

Innovation

• sequential circuits
• hardware model checking
• program verification
• intermediate representation
• C-to-circuit translation