A Customized Memory-aware Architecture for Biological Sequence Alignment

2025-07-29

AI Summary

Biological sequence alignment on conventional parallel platforms (e.g., GPUs) suffers from memory-bandwidth bottlenecks, limiting throughput and increasing power consumption. To address this, we propose a memory-aware near-data processing architecture tailored for 3D DRAM. Our approach innovatively embeds the dynamic programming alignment kernel directly into the DRAM logic layer, realizing a processing-in-memory (PIM) design that jointly exploits fine-grained (cell-level) and coarse-grained (block-level) parallelism to tightly integrate computation and storage. This architecture effectively mitigates the “memory wall” by drastically reducing data movement overhead while preserving high parallelism. Experimental evaluation demonstrates up to 2.4× speedup over state-of-the-art GPU-based implementations, with an average 37% reduction in power consumption—yielding substantial improvements in both throughput and energy efficiency.

Technology Category

• Machine Learning: Hardware-aware ML
• Data Mining & Knowledge Management: Scalability, Parallel & Distributed Systems
• Computer Vision: 3D Computer Vision

Application Category

• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Systems and Infrastructure for Web, Mobile and WoT: Data management and stream processing for Web, mobile and wireless applications
• User Modeling, Personalization and Recommendation: On-Device user modeling, personalization, and recommendation

Abstract

Sequence alignment is a fundamental process in computational biology which identifies regions of similarity in biological sequences. With the exponential growth in the volume of data in bioinformatics databases, the time, processing power, and memory bandwidth for comparing a query sequence with the available databases grows proportionally. The sequence alignment algorithms often involve simple arithmetic operations and feature high degrees of inherent fine-grained and coarse-grained parallelism. These features can be potentially exploited by a massive parallel processor, such as a GPU, to increase throughput. In this paper, we show that the excessive memory bandwidth demand of the sequence alignment algorithms prevents exploiting the maximum achievable throughput on conventional parallel machines. We then propose a memory-aware architecture to reduce the bandwidth demand of the sequence alignment algorithms, effectively pushing the memory wall to extract higher throughput. The design is integrated at the logic layer of an emerging 3D DRAM as a processing-in-memory architecture to further increase the available bandwidth. The experimental results show that the proposed architecture results in up to 2.4x speedup over a GPU-based design. Moreover, by moving the computation closer to the memory, power consumption is reduced by 37%, on average.

Problem

• Reducing memory bandwidth demand in sequence alignment algorithms
• Enhancing throughput via memory-aware parallel processing architecture
• Optimizing power efficiency by computation-in-memory approach

Innovation

• Customized memory-aware architecture for alignment
• Processing-in-memory with 3D DRAM integration
• Reduces bandwidth demand and power consumption