Dynamically Reprogrammable Runtime Monitors for Bounded-time MTL

2026-03-20

AI Summary

This work proposes a standard-cell-based, dynamically reprogrammable runtime monitor integrated on the same die as the system under verification, addressing the challenge of achieving in-speed, online monitoring with dynamic updates in high-performance processor systems. For the first time, bounded metric temporal logic (MTL) monitoring with field-updatable specifications is realized using standard-cell circuitry. The monitor operates synchronously with the host processor and supports post-deployment updates of monitoring properties via I/O pins. Its programmable architecture implements five primitive operations and queue-update rules that precisely capture the semantics of discrete-time bounded MTL. Simulation results demonstrate that a monitor supporting 16 atomic propositions occupies only 0.55 mm² and achieves a clock frequency of 1.25 GHz, exhibiting high efficiency, compactness, and dynamic reconfigurability.

Technology Category

Machine Learning: Hardware-aware MLCognitive Modeling & Cognitive Systems: Agent ArchitecturesPlanning, Routing, and Scheduling: Plan Execution and Monitoring

Application Category

Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterizationSecurity and Privacy: Large-scale security measurementsGraph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs

Abstract

A Runtime Verification (RV) framework that supports online, at-speed verification of properties that can change dynamically (during in-field operations) will benefit a large variety of applications. Several state-of-the-art RV frameworks propose to implement monitors on FPGAs. While this approach can support changes to the property being monitored during in-field operations, they struggle to keep pace with the system under verification which use high-performance processors. In this work, we propose a novel, reprogrammable monitor that is implemented using standard cells instead of FPGAs. This allows the monitor to be co-located with the system under verification (on the same die), and hence is amenable to at-speed monitoring of properties. Our proposed design consists of a programmable unit that implements five basic operations and a set of queue-update rules. We show that a composition of such programmable units faithfully implements discrete time, bounded MTL. We demonstrate through simulations that our proposed monitor can be reprogrammed (through its I/O pins) post deployment. A fairly large monitor which can support MTL formulae upto 16 atomic propositions occupies only 0.55 mm^2, while operating at a frequency of 1.25 GHz.

Problem

• Runtime Verification
• MTL
• Reprogrammable Monitor
• At-speed Monitoring
• High-performance Processors

Innovation

• Runtime Verification
• Metric Temporal Logic (MTL)
• Standard-cell Implementation
• At-speed Monitoring
• Dynamically Reprogrammable