Design Space Exploration of Embedded SoC Architectures for Real-Time Optimal Control

2024-10-16

arXiv.org

AI Summary

Real-time optimal control (e.g., model predictive control) for resource-constrained robots faces hardware bottlenecks in latency, energy efficiency, and computational density. Method: This paper proposes a hardware–software co-design methodology for embedded SoC architecture space exploration, centered on robotic control workloads. It introduces a quantitative evaluation framework integrating kernel-level benchmarks with end-to-end task-driven analysis (e.g., motion control, manipulation), coupled with hardware modeling, software stack optimization, and a custom compiler-enabled automated code generation pipeline. Contribution/Results: The work systematically compares scalar CPUs, vector processors, and domain-specific accelerators across performance, area, and utilization trade-offs—revealing that dedicated accelerators reduce control latency and improve energy efficiency by over 3.2× versus general-purpose processors. Furthermore, the developed mapping and code-generation toolchain demonstrates strong reusability across robotic control applications.

Technology Category

Machine Learning: Hardware-aware MLIntelligent Robots: Learning & Optimization for ROBSearch and Optimization: Mixed Discrete/Continuous Search

Application Category

Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterizationResponsible Web: Machine-in-the-loop, human agency and autonomyEconomics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems

Abstract

Empowering resource-limited robots to execute computationally intensive tasks such as locomotion and manipulation is challenging. This project provides a comprehensive design space exploration to determine optimal hardware computation architectures suitable for model-based control algorithms. We profile and optimize representative architectural designs across general-purpose scalar, vector processors, and specialized accelerators. Specifically, we compare CPUs, vector machines, and domain-specialized accelerators with kernel-level benchmarks and end-to-end representative robotic workloads. Our exploration provides a quantitative performance, area, and utilization comparison and analyzes the trade-offs between these representative distinct architectural designs. We demonstrate that architectural modifications, software, and system optimization can alleviate bottlenecks and enhance utilization. Finally, we propose a code generation flow to simplify the engineering work for mapping robotic workloads to specialized architectures.

Problem

• Optimizing hardware architectures for real-time robotic control algorithms
• Characterizing performance of embedded SoCs for model predictive control
• Reducing computational bottlenecks in resource-constrained robotic systems

Innovation

• Optimizing hardware computation architectures for control algorithms
• Profiling CPUs, vector processors, and specialized accelerators
• Proposing code generation flow for robotic workload mapping