Accelerating Post-Quantum Cryptography via LLM-Driven Hardware-Software Co-Design

2026-02-10

AI Summary

This work proposes a novel approach to accelerating the post-quantum cryptographic signature scheme FALCON on FPGA by integrating large language models (LLMs) into the hardware design flow. Given the computational complexity of post-quantum algorithms and the challenges in achieving efficient hardware implementations, the authors leverage an LLM to automatically identify performance-critical modules and generate optimized hardware descriptions within a high-level synthesis (HLS) framework. The methodology incorporates a human-in-the-loop mechanism to guide the LLM, enabling effective hardware-software co-optimization. Experimental results demonstrate that the LLM-generated accelerator cores achieve up to 2.6× speedup in execution time compared to conventional HLS-based designs, exhibit shorter critical paths, and significantly reduce development cycles while maintaining high design quality.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Learning to Search
• Humans and AI: Human-in-the-loop Machine Learning

Application Category

• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs

Abstract

Post-quantum cryptography (PQC) is crucial for securing data against emerging quantum threats. However, its algorithms are computationally complex and difficult to implement efficiently on hardware. In this paper, we explore the potential of Large Language Models (LLMs) to accelerate the hardware-software co-design process for PQC, with a focus on the FALCON digital signature scheme. We present a novel framework that leverages LLMs to analyze PQC algorithms, identify performance-critical components, and generate candidate hardware descriptions for FPGA implementation. We present the first quantitative comparison between LLM-driven synthesis and conventional HLS-based approaches for low-level compute-intensive kernels in FALCON, showing that human-in-the-loop LLM-generated accelerators can achieve up to 2.6x speedup in kernel execution time with shorter critical paths, while highlighting trade-offs in resource utilization and power consumption. Our results suggest that LLMs can minimize design effort and development time by automating FPGA accelerator design iterations for PQC algorithms, offering a promising new direction for rapid and adaptive PQC accelerator design on FPGAs.

Problem

• Post-Quantum Cryptography
• Hardware-Software Co-Design
• FPGA Acceleration
• FALCON
• Computational Complexity

Innovation

• LLM-driven co-design
• Post-Quantum Cryptography
• FALCON
• FPGA acceleration
• Hardware-software co-design