RTLScout: Joint Agentic Code and Synthesis Optimization for Efficient Digital Circuits

2026-06-03

AI Summary

This work addresses the inefficiency of traditional RTL design flows in optimizing power, performance, and area (PPA), which struggle to automatically explore high-quality implementations. The authors propose an iterative optimization framework that integrates large language model (LLM) agents with circuit-level synthesis. By leveraging a multi-round elite pool mechanism, the approach combines LLM-generated RTL code, gate-level rewriting, and arithmetic architecture search, guided by PPA metrics from Yosys/OpenROAD to iteratively evolve designs. Experimental results on the ASAP7 technology node demonstrate that the method achieves a 35% reduction in area and a 45% decrease in delay for an IEEE-754-compliant 16-bit floating-point multiplier, significantly outperforming reference designs produced by commercial tools across the Pareto front. These findings validate the effectiveness of synergistically coupling high-level intelligent guidance with low-level physical optimization.

Abstract

We present RTLScout, an autonomous system that combines LLM-driven agentic design with circuit-level synthesis optimization and arithmetic architecture sweeps. An LLM agent iteratively writes, evaluates, and refines RTL designs using tool calls, guided by quantitative PPA (power, performance, area) feedback from Yosys and OpenROAD. We introduce a multi-run elite pool framework, where the best designs and lessons learned seed subsequent agent runs. The pipeline comprises four complementary phases: agentic code optimization, agentic gate-level rewriting, arithmetic architecture sweeps, and an optional high-effort gate-level refinement pass. On an IEEE-754-compliant 16-bit floating-point multiplier with subnormal support, RTLScout reduces area by 35% and delay by 45% relative to a starting design synthesized in ASAP7 technology. Each phase provides distinct improvements, and high-effort gate-level optimization is most effective as a refinement of already well-optimized designs rather than a substitute for earlier stages. The resulting Pareto front outperforms a commercial-tool reference design on the same technology.

Problem

• RTL optimization
• circuit synthesis
• PPA optimization
• digital circuits
• arithmetic architecture

Innovation

• LLM agent
• RTL optimization
• synthesis-aware design
• arithmetic architecture search
• PPA feedback