EasySize: Elastic Analog Circuit Sizing via LLM-Guided Heuristic Search

2025-08-07

AI Summary

Analog circuit sizing optimization suffers from poor generalizability, difficulty in cross-node transfer, heavy reliance on expert knowledge, and prohibitively high simulation costs. Method: This paper proposes EasySize—a gate-level sizing optimization framework leveraging a fine-tuned lightweight large language model (Qwen3-8B). Its core innovations include: (i) the first integration of LLM-guided heuristic search with dynamically constructed task-specific loss, enabling zero-retraining cross-node migration via performance attainability disparity; and (ii) adaptive search strategy adjustment within a feedback-enhanced loop by synergistically combining differential evolution and particle swarm optimization. Results: Trained solely on 350 nm data, EasySize achieves an 86.67% higher task completion rate and reduces simulation resource consumption by over 96.67% compared to AutoCkt on op-amp circuits across 180 nm to 22 nm technology nodes.

Technology Category

• Search and Optimization: Sampling/Simulation-based Search
• Machine Learning: Optimization
• Constraint Satisfaction and Optimization: Search

Application Category

• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs

Abstract

Analog circuit design is a time-consuming, experience-driven task in chip development. Despite advances in AI, developing universal, fast, and stable gate sizing methods for analog circuits remains a significant challenge. Recent approaches combine Large Language Models (LLMs) with heuristic search techniques to enhance generalizability, but they often depend on large model sizes and lack portability across different technology nodes. To overcome these limitations, we propose EasySize, the first lightweight gate sizing framework based on a finetuned Qwen3-8B model, designed for universal applicability across process nodes, design specifications, and circuit topologies. EasySize exploits the varying Ease of Attainability (EOA) of performance metrics to dynamically construct task-specific loss functions, enabling efficient heuristic search through global Differential Evolution (DE) and local Particle Swarm Optimization (PSO) within a feedback-enhanced flow. Although finetuned solely on 350nm node data, EasySize achieves strong performance on 5 operational amplifier (Op-Amp) netlists across 180nm, 45nm, and 22nm technology nodes without additional targeted training, and outperforms AutoCkt, a widely-used Reinforcement Learning based sizing framework, on 86.67% of tasks with more than 96.67% of simulation resources reduction. We argue that EasySize can significantly reduce the reliance on human expertise and computational resources in gate sizing, thereby accelerating and simplifying the analog circuit design process. EasySize will be open-sourced at a later date.

Problem

• Develops universal analog circuit sizing method
• Reduces reliance on human expertise
• Improves portability across technology nodes

Innovation

• Lightweight Qwen3-8B model for universal gate sizing
• Dynamic EOA-based loss functions for heuristic search
• Hybrid DE-PSO optimization in feedback-enhanced flow