🤖 AI Summary
Irregular tensor computations in high-performance computing (HPC)—such as those in conjugate gradient methods—suffer from low data reuse due to irregular operator shapes and complex dependency-directed acyclic graphs (DAGs), hindering co-optimization between conventional schedulers and hardware. To address this, we propose a software-hardware co-design acceleration architecture. Our key contributions are: (1) CHORD, a novel hybrid on-chip buffer mechanism supporting both implicit and explicit data management; (2) SCORE, a DAG-aware scheduler that enables fine-grained reuse exploitation across tensor operations in a DAG; and (3) tight integration of tensor algebra compilation optimizations with a customized microarchitecture. Evaluated on representative HPC workloads, our architecture achieves a 4.0× geometric mean speedup and 4.0× energy efficiency improvement over state-of-the-art accelerators, significantly overcoming the data reuse bottleneck in irregular tensor computations.
📝 Abstract
Tensor algebra accelerators have been gaining popularity for running high-performance computing (HPC) workloads. Identifying optimal schedules for individual tensor operations and designing hardware to run these schedules is an active area of research. Unfortunately, operators in HPC workloads such as Conjugate Gradient often have operators with skewed shapes, fundamentally limiting the reuse any schedule can leverage. Moreover, the operators form a complex DAG of dependencies, making it challenging to apply simple fusion/pipelining techniques to extract inter-operation reuse. To address these challenges, this work proposes an accelerator CELLO. CELLO uses a novel on-chip buffer mechanism called CHORD co-designed with a novel scheduler called SCORE, which together enables identifying and exploiting reuse over complex DAGs of tensor operations. CELLO provides 4x geomean speedup and 4x energy efficiency over state-of-the-art accelerators across HPC workloads.
