🤖 AI Summary
This work addresses the severe performance bottleneck imposed by fine-grained atomic updates in particle-in-cell simulations on conventional multicore CPUs. Targeting modern CPU architectures featuring mixed MPU-VPU SIMD units, the authors propose the first holistic co-design for current deposition, centered on matrix outer products. The approach integrates blocked matrix algorithms, a hybrid execution pipeline, an incremental sorter with O(1) amortized complexity, and a gap-compressed memory layout to optimize data access. Evaluated on laser wakefield acceleration simulations, the method achieves an 8.7× speedup in the third-order deposition kernel—reaching 83.08% of the CPU’s theoretical peak performance—and delivers a 2.63× end-to-end runtime acceleration, substantially outperforming existing GPU implementations.
📝 Abstract
Particle-in-Cell (PIC) simulations spend most of their execution time on particle--grid interactions, where fine-grained atomic updates become a major bottleneck on traditional many-core CPUs. Recent CPU architectures integrate specialized Matrix Processing Units (MPUs) that efficiently support matrix outer-product operations, offering new opportunities to overcome this limitation. Leveraging this architectural shift, this work focuses on redesigning the current deposition step of PIC simulations under a matrix-centric execution model. We present MatrixPIC, the first holistic co-design of the deposition kernel, data layout, and incremental particle sorting tailored to the hybrid MPU--VPU SIMD model on modern CPUs. MatrixPIC introduces: (i)~a block-matrix formulation of the current deposition algorithm that maps naturally to MPU outer-product primitives; (ii)~a hybrid execution pipeline that combines MPU-based high-density accumulation with VPU-based data preparation and control flow; and (iii)~an $O(1)$-amortized incremental sorter based on a gapped packed-memory array to preserve data locality for efficient MPU execution. Evaluated on a next-generation HPC platform, MatrixPIC achieves significant performance gains. In Laser-Wakefield Acceleration (LWFA) simulations, it delivers up to $2.63\times$ speedup in total runtime. For third-order deposition, the core kernel is accelerated by $8.7\times$ over the baseline and $2.0\times$ over the best hand-optimized VPU implementation. Moreover, MatrixPIC reaches $83.08\%$ of theoretical CPU peak performance, nearly $2.8\times$ higher than a highly optimized CUDA kernel on a data center GPU. These results demonstrate the effectiveness of matrix-oriented co-design for accelerating PIC simulations on emerging CPU architectures.