An ASIC Emulated Oscillator Ising/Potts Machine Solving Combinatorial Optimization Problems

2026-04-15

AI Summary

This work addresses the limitations of existing approaches for simulating oscillator-based Ising/Potts machines—namely, low coupling precision, process sensitivity, poor scalability in analog designs, and high energy consumption with irregular memory access in digital platforms—by proposing a co-designed algorithm-hardware architecture implemented as a custom ASIC. Leveraging a fixed-point Kuramoto model, the architecture efficiently emulates Ising/Potts dynamics through a directly connected array of processing units interconnected via a king’s graph topology, thereby eliminating shared-memory bottlenecks and circumventing the memory wall while retaining programmability. A 20×20 prototype chip achieves solution accuracies of 97%–100% on Max-Cut and graph coloring benchmarks, significantly outperforming general-purpose platforms in both energy efficiency and solution speed.

Technology Category

Machine Learning: Hardware-aware MLConstraint Satisfaction and Optimization: Distributed CSP/OptimizationSearch and Optimization: Sampling/Simulation-based Search

Application Category

Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphsEconomics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystemsUser Modeling, Personalization and Recommendation: On-Device user modeling, personalization, and recommendation

Abstract

Oscillator-based Ising/Potts machines (OIMs/OPMs) are promising hardware accelerators for NP-hard combinatorial optimization problems using coupled oscillator synchronization dynamics. Analog OIMs/OPMs offer speed advantages but have limited coupling resolution, process variation susceptibility, and scalability issues, while digital GPU/CPU emulations provide flexibility but suffer from irregular memory access patterns and energy inefficiency. This work presents a custom ASIC architecture that digitally emulates OIM/OPM dynamics using simplified fixedpoint Kuramoto model equations. The scalable design features processing elements with direct interconnections, eliminating shared memory bottleneck while maintaining digital programmability and precision. A 20x20 processing element array with king's graph connectivity is prototyped and evaluated via post-layout simulations on unweighted/weighted max-cut and graph coloring problems, achieving 97-100% maximum accuracy with significant speed and energy improvements over general-purpose platforms, demonstrating the viability of algorithmically codesigned ASICs.

Problem

• combinatorial optimization
• Ising machine
• Potts machine
• hardware accelerator
• NP-hard problems

Innovation

• ASIC
• Oscillator-based Ising Machine
• Kuramoto model
• Combinatorial Optimization
• Digital Emulation