ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis

2025-08-17

AI Summary

In VLSI design, post-placement power simulation is time-consuming and severely hinders early-stage optimization. This paper proposes the first self-supervised, cross-stage modeling method that predicts fine-grained timing-aware power directly from gate-level netlists—without requiring placement information. Our approach introduces a novel graph neural network architecture tailored for circuit power modeling, integrating structural and timing feature extraction, cross-stage feature alignment, and grouped power prediction. We further design a dedicated pretraining-fine-tuning paradigm to ensure generalization across diverse designs. Experimental results demonstrate high accuracy: mean absolute percentage error (MAPE) of <1% for total power, and 0.58%, 0.45%, and 5.12% for clock-tree, register, and combinational-logic modules, respectively. Moreover, inference speed significantly surpasses that of commercial standard flows.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Generative Adversarial Networks (GANs) for Vision
• Planning, Routing, and Scheduling: Planning with Language Models

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Web Mining and Content Analysis: Large pretrained models with web data
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs

Abstract

Accurate power prediction in VLSI design is crucial for effective power optimization, especially as designs get transformed from gate-level netlist to layout stages. However, traditional accurate power simulation requires time-consuming back-end processing and simulation steps, which significantly impede design optimization. To address this, we propose ATLAS, which can predict the ultimate time-based layout power for any new design in the gate-level netlist. To the best of our knowledge, ATLAS is the first work that supports both time-based power simulation and general cross-design power modeling. It achieves such general time-based power modeling by proposing a new pre-training and fine-tuning paradigm customized for circuit power. Targeting golden per-cycle layout power from commercial tools, our ATLAS achieves the mean absolute percentage error (MAPE) of only 0.58%, 0.45%, and 5.12% for the clock tree, register, and combinational power groups, respectively, without any layout information. Overall, the MAPE for the total power of the entire design is <1%, and the inference speed of a workload is significantly faster than the standard flow of commercial tools.

Problem

• Accurate power prediction in VLSI design optimization
• Time-consuming traditional power simulation methods
• Cross-design time-based power modeling without layout info

Innovation

• Self-supervised pre-training for circuit power
• Cross-stage netlist to layout power prediction
• Time-based power modeling without layout info