CMOS-integrated superparamagnetic tunnel junction-based p-bit

2026-04-15

AI Summary

This work addresses the demand for scalable probabilistic computing hardware by proposing and demonstrating a monolithic integration of superparamagnetic tunnel junctions (sMTJs) with 130 nm CMOS technology to realize tunable probabilistic bits (p-bits). Leveraging the intrinsic thermal-fluctuation-induced resistance variations of sMTJs, the designed p-bit cell generates output voltages that can be modulated by input signals, thereby achieving both true randomness and controllability at the hardware level. This study represents the first successful integration of sMTJs on a 130 nm CMOS platform and experimentally validates their feasibility as tunable p-bits. The results establish a critical device foundation and circuit paradigm for the development of large-scale, CMOS-compatible probabilistic computing chips.

Technology Category

Machine Learning: Probabilistic Circuits and Graphical ModelsReasoning under Uncertainty: Probabilistic ProgrammingCognitive Modeling & Cognitive Systems: Neural Spike Coding

Application Category

Security and Privacy: Large-scale security measurementsSystems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applicationsResponsible Web: Data and user privacy-enhancing technologies for the Web

Abstract

Probabilistic computers offer promising solutions for computationally hard problems in domains such as combinatorial optimization and machine learning. A key building block in these systems is the probabilistic bit (p-bit), which relies on superparamagnetic tunnel junctions (sMTJs) as its source of randomness. A challenging threshold to cross for scaling sMTJ-based p-bit systems is integration of sMTJs with CMOS technology. In this work, we present experimental results of a p-bit unit cell using sMTJs integrated with 130 nm CMOS technology and demonstrate that the sMTJ's resistance fluctuations can generate a corresponding fluctuating digital output voltage which is tunable via the input voltage. These findings establish the feasibility of CMOS-compatible, sMTJ-based probabilistic circuits and mark a key step toward scalable hardware for real-world probabilistic computing applications.

Problem

• probabilistic computing
• p-bit
• superparamagnetic tunnel junction
• CMOS integration
• hardware scalability

Innovation

• superparamagnetic tunnel junction
• probabilistic computing
• CMOS integration
• p-bit
• stochastic hardware