🤖 AI Summary
To address the challenges of high topology dynamics and load-balancing measurement in low Earth orbit (LEO) mega-constellations caused by rapid satellite mobility, this paper proposes an end-to-end, low-overhead network measurement architecture. Methodologically, it introduces (1) a lightweight digital twin system that predicts future topologies and pre-distributes collision-free hash seeds, and (2) a bit-operation-optimized, onboard port-aggregation data structure that eliminates hash collisions and compresses state storage. The design is efficiently implemented on FPGA. Evaluation shows an average 70% reduction in memory footprint and a 90% decrease in relative measurement error. This work is the first to jointly integrate digital twin–driven prediction with collision-free hash scheduling for LEO network measurement, significantly enhancing the scalability and accuracy of per-flow load balancing (PFLB) under highly dynamic conditions.
📝 Abstract
The high mobility of satellites in Low Earth Orbit (LEO) mega-constellations induces a highly dynamic network topology, leading to many problems like frequent service disruptions. To mitigate this, Packet-based Load Balancing (PBLB) is employed. However, this paradigm shift introduces two critical challenges for network measurement stemming from the requirement for port-level granularity: memory inflation and severe hash collisions. To tackle these challenges, we propose CountingStars, a low-overhead network-wide measurement architecture. In the ground controller, CountingStars builds a digital twins system to accurately predict the future network topology. This allows ground controller to generate and distribute collision-free hash seeds to satellites in advance. On the satellite, we introduce a port aggregation data structure that decouples the unique flow identifier from its multi-port counter and updates it through efficient bit operations, solving the memory inflation caused by PBLB. Simulation results show that the memory usage of CountingStars is reduced by 70% on average, and the relative error of measurement is reduced by 90% on average. Implementation on FPGA shows its prospect to deploy in real system.