QuadINR: Hardware-Efficient Implicit Neural Representations Through Quadratic Activation

2025-08-19

AI Summary

To address spectral bias in implicit neural representations (INRs), which limits high-frequency signal modeling, and the high hardware overhead of existing activation functions, this paper proposes QuadINR. It employs a piecewise quadratic activation function that introduces rich harmonic components while maintaining low hardware complexity, thereby effectively mitigating spectral bias; combined with an N-stage unified pipelined architecture, it enables efficient compute–memory co-design. Theoretically, its superior spectral properties are validated via neural tangent kernel analysis. Hardware-wise, QuadINR is end-to-end deployed on both FPGA (Xilinx VCU128) and a 28 nm ASIC. Experiments demonstrate a 2.06 dB PSNR improvement in image/video reconstruction tasks. The ASIC occupies only 1914 μm², consumes 6.14 mW dynamic power, reduces resource and power consumption by 97% versus baselines, and cuts latency by 93%, achieving, for the first time, a unified design of high-fidelity representation and ultra-low-power hardware deployment.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Representation Learning for Vision
• Knowledge Representation and Reasoning: Qualitative Reasoning

Application Category

• Search and Retrieval-Augmented AI: Web query analysis, representation and understanding
• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• Graph Algorithms and Modeling for the Web: Graph embeddings and representation learning for Web-related graphs

Abstract

Implicit Neural Representations (INRs) encode discrete signals continuously while addressing spectral bias through activation functions (AFs). Previous approaches mitigate this bias by employing complex AFs, which often incur significant hardware overhead. To tackle this challenge, we introduce QuadINR, a hardware-efficient INR that utilizes piecewise quadratic AFs to achieve superior performance with dramatic reductions in hardware consumption. The quadratic functions encompass rich harmonic content in their Fourier series, delivering enhanced expressivity for high-frequency signals, as verified through Neural Tangent Kernel (NTK) analysis. We develop a unified $N$-stage pipeline framework that facilitates efficient hardware implementation of various AFs in INRs. We demonstrate FPGA implementations on the VCU128 platform and an ASIC implementation in a 28nm process. Experiments across images and videos show that QuadINR achieves up to 2.06dB PSNR improvement over prior work, with an area of only 1914$μ$m$^2$ and a dynamic power of 6.14mW, reducing resource and power consumption by up to 97% and improving latency by up to 93% vs existing baselines.

Problem

• Reducing hardware overhead of complex activation functions
• Enhancing expressivity for high-frequency signal representation
• Achieving efficient FPGA and ASIC implementation with low power

Innovation

• Quadratic activation functions for efficiency
• Unified pipeline framework for hardware implementation
• Dramatic resource and power consumption reduction