Fast and Accurate RFIC Performance Prediction via Pin Level Graph Neural Networks and Probabilistic Flow

2025-08-22

AI Summary

To address the high computational cost of traditional RF circuit simulation and the strong data dependency and poor cross-topology generalization of existing machine learning models, this paper proposes a lightweight, data-efficient, topology-aware graph probabilistic modeling framework. We innovatively construct a pin-level circuit graph representation and integrate a graph neural network (GNN) with a masked autoregressive flow (MAF) model: the GNN enables fine-grained connectivity modeling and message passing, while the MAF accurately captures nonlinear, multimodal performance distributions. The method significantly reduces data requirements, achieving an average sMAPE of 2.40% and MRE of 2.91% across diverse RF circuits. Compared to the prior state-of-the-art, it improves MRE by 3.14× and reduces training sample count by 2.24×. This work establishes a new paradigm for high-accuracy, low-overhead surrogate modeling in RFIC design automation.

Technology Category

• Machine Learning: Probabilistic Circuits and Graphical Models
• Reasoning under Uncertainty: Relational Probabilistic Models
• Planning, Routing, and Scheduling: Model-Based Reasoning

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• User Modeling, Personalization and Recommendation: On-Device user modeling, personalization, and recommendation
• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications

Abstract

Accurately predicting the performance of active radio frequency (RF) circuits is essential for modern wireless systems but remains challenging due to highly nonlinear, layout-sensitive behavior and the high computational cost of traditional simulation tools. Existing machine learning (ML) surrogates often require large datasets to generalize across various topologies or to accurately model skewed and multi-modal performance metrics. In this work, a lightweight, data-efficient, and topology-aware graph neural network (GNN) model is proposed for predicting key performance metrics of multiple topologies of active RF circuits such as low noise amplifiers (LNAs), mixers, voltage-controlled oscillators (VCOs), and PAs. To capture transistor-level symmetry and preserve fine-grained connectivity details, circuits are modeled at the device-terminal level, enabling scalable message passing while reducing data requirements. Masked autoregressive flow (MAF) output heads are incorporated to improve robustness in modeling complex target distributions. Experiments on datasets demonstrate high prediction accuracy, with symmetric mean absolute percentage error (sMAPE) and mean relative error (MRE) averaging 2.40% and 2.91%, respectively. Owing to the pin-level conversion of circuit to graph and ML architecture robust to modeling complex densities of RF metrics, the MRE is improved by 3.14x while using 2.24x fewer training samples compared to prior work, demonstrating the method's effectiveness for rapid and accurate RF circuit design automation.

Problem

• Predicting active RF circuit performance with high accuracy
• Reducing data requirements for machine learning surrogates
• Modeling complex distributions of multi-modal RF metrics

Innovation

• Pin-level graph neural network modeling
• Masked autoregressive flow output heads
• Device-terminal level circuit representation