🤖 AI Summary
This work addresses the communication bottleneck caused by frequent inter-device synchronization in multi-GPU tensor-parallel inference, which limits scalability. The authors propose the Parallel Track Transformer architecture, featuring an innovative parallel-track computation structure and a novel task partitioning and scheduling strategy that substantially reduces cross-device dependencies while preserving model quality. Implemented within the TensorRT-LLM and vLLM frameworks, the approach achieves up to a 16-fold reduction in synchronization operations, decreases first-token latency by 15–30%, reduces per-token generation time by 2–12%, and improves throughput by as much as 31.9%.
📝 Abstract
Efficient large-scale inference of transformer-based large language models (LLMs) remains a fundamental systems challenge, frequently requiring multi-GPU parallelism to meet stringent latency and throughput targets. Conventional tensor parallelism decomposes matrix operations across devices but introduces substantial inter-GPU synchronization, leading to communication bottlenecks and degraded scalability. We propose the Parallel Track (PT) Transformer, a novel architectural paradigm that restructures computation to minimize cross-device dependencies. PT achieves up to a 16x reduction in synchronization operations relative to standard tensor parallelism, while maintaining competitive model quality in our experiments. We integrate PT into two widely adopted LLM serving stacks-Tensor-RT-LLM and vLLM-and report consistent improvements in serving efficiency, including up to 15-30% reduced time to first token, 2-12% reduced time per output token, and up to 31.90% increased throughput in both settings.