MCHA: A Memory-Centric Hierarchical Architecture for Parallel-Sequential Computing

2026-08-05

AI Summary

This work addresses severe cache saturation and memory bandwidth bottlenecks in parallel-serial computing tasks—such as multi-agent reinforcement learning (MARL)—caused by irregular memory access patterns. To this end, the authors propose MCHA, a novel reconfigurable hardware architecture featuring a storage-centric hierarchical design that co-optimizes the parallel-serial programming model. MCHA employs a hierarchical interconnect for distributed inter-core routing and integrates an event-driven, condition-triggered mechanism to effectively hide communication latency. Evaluated on MARL workloads, MCHA achieves speedups of 153× to 2457× over an A100 GPU, reduces main memory access from 96% to 5.44%, and occupies only 2.92 mm² with a power consumption of 115.36 mW at 200 MHz in 28 nm technology.

Abstract

Emerging workloads, such as Multi-Agent Reinforcement Learning (MARL), large-scale neuromorphic computing, and probabilistic graphical models, intrinsically exhibit parallel-sequential computing patterns. While these tasks demand massive parallelism to achieve high throughput, they are severely bottlenecked by irregular data access patterns centralized to main memory. Consequently, conventional architectures face fundamental limitations when executing these workloads, primarily manifesting as global buffer saturation and memory-bound bottlenecks. To address these challenges, we propose the Memory-Centric Hierarchical Architecture (MCHA), a reconfigurable hardware solution tailored for parallel-sequential execution. MCHA leverages a hierarchical communication strategy that facilitates distributed, inter-core data routing, thereby significantly reducing the bandwidth burden on the global memory. Complementing the hardware, MCHA introduces a novel parallel-sequential programming model that utilizes event-driven conditional triggers to effectively hide data transmission latency within the execution pipeline. We benchmark MCHA against a diverse suite of parallel-sequential tasks, including MARL, motor variable control, and Markov random fields. Validated through our open-source, cycle-accurate simulator, MCHA demonstrates performance speedups ranging from 153.06$\times$ to 2456.96$\times$ over NVIDIA A100 GPUs on MARL workloads, while maintaining robust programming flexibility across other application domains. Furthermore, the architecture successfully reduces main memory access from 96% to 5.44%. When synthesized in a 28 nm process, the MCHA implementation occupies an area footprint of 2.92mm$^2$ and consumes 115.36 mW of power at 200 MHz. MCHA is open-sourced at https://github.com/carabdis/MCHA.

Problem

• parallel-sequential computing
• memory bottleneck
• irregular data access
• throughput
• main memory

Innovation

• Memory-Centric Architecture
• Parallel-Sequential Computing
• Hierarchical Communication
• Event-Driven Programming Model
• Distributed Data Routing