Hardware Design and Security in the Era of Chiplets and LLMs

2026-08-05

AI Summary

This work addresses emerging hardware security threats introduced by heterogeneous chiplet systems and large language model (LLM)-driven EDA flows, which span architectural, logical, and physical layers. For the first time, it presents a unified model of multi-level security risks in co-design scenarios involving chiplets and LLMs. The study proposes a physically isolated root-of-trust architecture that integrates 2.5D split manufacturing with active interposers, alongside native defense mechanisms tailored for LLM-EDA pipelines. A comprehensive security analysis framework demonstrates the effectiveness of this co-design defense paradigm in ensuring hardware integrity and trustworthiness throughout the design flow, offering a novel pathway toward secure next-generation chip design.

Abstract

The semiconductor industry is undergoing a dual revolution: the shift toward heterogeneous 2.5D chiplet systems and the integration of Large Language Models (LLMs) into Electronic Design Automation (EDA) flows. While these paradigms offer unprecedented benefits in yield, modularity, design productivity, etc., they radically expand the hardware attack surface. This paper provides a unified analysis of these frontiers, ranging from attacks on chiplet systems (including hardware stacks for LLM acceleration) across architectural, logical, and physical levels, to various exploits against LLM-driven EDA pipelines. To secure chiplet systems, we review a powerful defense approach that leverages 2.5D split manufacturing and active interposers for physically isolated Root of Trust (RoT) architectures. To secure LLM-driven EDA pipelines, we first identify native threats and then review state-of-the-art defense techniques. Finally, we discuss how LLM systems can advance hardware security efforts for modern systems, including chiplets.

Problem

• chiplets
• Large Language Models
• hardware security
• Electronic Design Automation
• attack surface

Innovation

• chiplets
• Large Language Models
• hardware security
• Root of Trust
• split manufacturing