TLGLock: A New Approach in Logic Locking Using Key-Driven Charge Recycling in Threshold Logic Gates

2025-08-25

AI Summary

Logic locking suffers from poor scalability and high hardware overhead. This paper proposes TLGLock—the first gate-level logic locking scheme that integrates threshold logic gates (TLGs) with key-driven charge recycling. By embedding keys into weighted logic functions and enabling dynamic charge sharing, TLGLock achieves stateless, compact, and tunable hardware security. Compared to conventional latch-based locking, TLGLock reduces area, delay, and power consumption by 30%, 50%, and 20%, respectively. It also improves resilience against SAT attacks by a factor of three and achieves 100% output corruption under incorrect keys. In terms of the joint security-overhead trade-off, TLGLock significantly outperforms mainstream approaches including XOR-based locking and SFLL-HD.

Technology Category

• Machine Learning: Hardware-aware ML
• Knowledge Representation and Reasoning: Logic Programming
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories

Application Category

• Security and Privacy: Large-scale security measurements
• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Responsible Web: Measurement, analysis, and circumvention of Web censorship

Abstract

Logic locking remains one of the most promising defenses against hardware piracy, yet current approaches often face challenges in scalability and design overhead. In this paper, we present TLGLock, a new design paradigm that leverages the structural expressiveness of Threshold Logic Gates (TLGs) and the energy efficiency of charge recycling to enforce key-dependent functionality at the gate level. By embedding the key into the gate's weighted logic and utilizing dynamic charge sharing, TLGLock provides a stateless and compact alternative to conventional locking techniques. We implement a complete synthesis-to-locking flow and evaluate it using ISCAS, ITC, and MCNC benchmarks. Results show that TLGLock achieves up to 30% area, 50% delay, and 20% power savings compared to latch-based locking schemes. In comparison with XOR and SFLL-HD methods, TLGLock offers up to 3x higher SAT attack resistance with significantly lower overhead. Furthermore, randomized key-weight experiments demonstrate that TLGLock can reach up to 100% output corruption under incorrect keys, enabling tunable security at minimal cost. These results position TLGLock as a scalable and resilient solution for secure hardware design.

Problem

• Enhancing hardware security against piracy with logic locking
• Reducing design overhead in conventional locking techniques
• Improving SAT attack resistance with lower energy consumption

Innovation

• Key-driven charge recycling in threshold logic gates
• Stateless compact locking via dynamic charge sharing
• Embedding keys into weighted gate logic