An Open-Source Flow for Single-Phase, Edge-Triggered to Two-Phase, Non-Overlapping Clocking Conversion

2026-05-06

AI Summary

Although two-phase clocking offers advantages in timing margin and flexibility, its adoption in RTL implementation and static timing closure has been hindered by the absence of an automated design flow. This work presents the first fully automated two-phase clocking methodology integrated into OpenROAD Flow Scripts, which automatically transforms flip-flop-based RTL into latch-based two-phase implementations. The flow encompasses technology mapping (Yosys), retiming (ABC), dual-clock-tree synthesis, functional correctness verification, and end-to-end RTL-to-GDS physical implementation. It supports both clock-gating and feedback-multiplexer latch architectures; the clock-gating variant reduces power consumption by 29.2% on average and halves the latch count. By enabling time borrowing, the proposed approach successfully achieves timing convergence on critical paths where the original flip-flop design fails to meet timing constraints.

Abstract

Two-phase clocking offers significant advantages in timing margin and clock flexibility, yet its adoption remains limited due to the absence of automation in modern design flows. Managing strict non-overlap and 180$^\circ$ phase separation introduces complexity in RTL implementation and timing closure, leaving two-phase clocking rare in practice. This paper presents the first fully automated two-phase clocking flow integrated into OpenROAD Flow Scripts (ORFS). Our methodology automatically transforms flip-flop-based RTL into two-phase latch-based designs using Yosys technology mapping, ABC retiming, dual clock tree synthesis, two-phase correctness validation, and full physical design from RTL-to-GDS. We implement clock-gated and recirculation mux variants, where clock-gated achieves an average 29.2\% power reduction and 50\% latch count reduction over recirculation mux. Both variants are compared against flip-flop baselines, demonstrating timing closure through time borrowing on a design that failed timing with flip-flops.

Problem

• two-phase clocking
• non-overlapping clocks
• timing closure
• RTL implementation
• clock automation

Innovation

• two-phase clocking
• non-overlapping clocks
• automated RTL-to-GDS flow
• latch-based design
• time borrowing