ScaleDisturb: Exploiting Temporal Asymmetry to Amplify Read Disturbance in Modern DRAM Chips

2026-06-05

AI Summary

This work addresses the growing vulnerability of high-density DRAM to read disturbance errors—such as RowHammer—exacerbated by aggressive technology scaling, noting that prior studies have explored only limited access patterns. The paper introduces ScaleDisturb, a novel approach that leverages temporal asymmetry by prolonging the activation duration of two aggressor rows to substantially amplify disturbance effects. Large-scale experiments across 196 DDR4 and three HBM2 chips demonstrate that ScaleDisturb significantly reduces the number of required row activations and enhances bit-flip success rates, particularly in advanced process nodes. The study further validates the attack’s practicality through a user-space implementation on real systems and evaluates the efficacy of four existing mitigation strategies.

Abstract

DRAM suffers from read disturbance phenomena (e.g., RowHammer and RowPress), where repeatedly accessing or continuously keeping open a DRAM row (aggressor row) induces bitflips in other physically nearby unaccessed rows (victim rows). The disturbance mechanism is practically exploitable from the software stack and worsens across generations with continued density scaling. DRAM read disturbance is highly sensitive to memory access patterns, yet prior work explores read disturbance under only a limited set of access patterns. We present ScaleDisturb, a new DRAM access pattern that can amplify DRAM read disturbance by asymmetrically extending the open time of two aggressor rows. Our rigorous experimental characterization of 196 DDR4 and 3 HBM2 DRAM chips shows that ScaleDisturb (1) leads to bitflips at significantly fewer row activations, compared to state-of-the-art memory access patterns, (2) makes read disturbance attacks easier across all tested DRAM chips, (3) increases DRAM vulnerability to read disturbance as DRAM manufacturing technology scales down to smaller node sizes. We showcase a proof-of-concept attack on a real system where a user-level program leveraging ScaleDisturb induces more bitflips than state-of-the-art RowHammer and RowPress memory access patterns. We describe and evaluate four solutions for mitigating read disturbance bitflips in the presence of ScaleDisturb and call for more research on the topic.

Problem

• read disturbance
• DRAM
• RowHammer
• memory access patterns
• bitflips

Innovation

• ScaleDisturb
• read disturbance
• temporal asymmetry
• RowHammer
• DRAM vulnerability