🤖 AI Summary
This work addresses the challenge of compiling for modular multi-quantum processor architectures by jointly optimizing local qubit connectivity and inter-QPU communication to mitigate communication congestion, port overloading, and imbalanced boundary qubit allocation. The authors propose QuPort, a compilation framework that explicitly models QPU communication port constraints and link congestion at the compiler level for the first time. QuPort introduces a three-layer graph model—comprising a logical interaction graph, a physical coupling graph, and a QPU interconnect graph—and devises a TPCCAP partitioning method that simultaneously optimizes cut-edge distance, port overflow, and link congestion. Through an integrated pipeline featuring port-aware placement, remote gate extraction, and topology-aware scheduling, QuPort significantly reduces inter-QPU communication overhead, balances port utilization, and enhances compilation efficiency without relying on hardware-specific protocols.
📝 Abstract
Modular quantum processors require a compiler to reason about two resources at the same time: local device connectivity and communication across QPUs. A mapping that is acceptable on a single coupling graph may be unsuitable for a modular machine if it creates excessive cross-QPU traffic, concentrates that traffic on a small number of interconnect links, or assigns many boundary qubits to a QPU with few communication ports. This paper presents QuPort, a Python and Qiskit-based compilation framework that studies this setting through an explicit three-level model: a weighted logical interaction graph, a directed physical coupling map, and an undirected QPU-level interconnect graph. The main partitioning method, TPCCAP, optimizes the implemented objective formed by weighted cut distance, communication-port overflow, and routed link-load congestion. The framework also includes heavy-edge clustering, balanced greedy partitioning, simulated-annealing refinement, communication-port-aware layout, extraction of remote two-qubit operations, local-only routing of per-QPU circuits, and topology-aware schedule estimation. The model is a compiler-level abstraction. It does not claim a calibrated hardware runtime or an implementation of a physical remote-gate protocol.