🤖 AI Summary
This study addresses the challenge that existing functional verification simulators struggle to efficiently generate large volumes of power traces under short-duration, minimally varied inputs, thereby hindering side-channel analysis during pre-silicon simulation. To overcome this limitation, this work proposes the first open-source Verilog simulator that integrates compiler-level performance, fully timed gate-level simulation, and runtime state manipulation capabilities. The tool enables multiple forked executions following a single initialization and supports pausing, inspecting, modifying, and reproducing simulation states without altering the design, thereby preserving precise timing and leakage characteristics. Experimental results demonstrate that the simulator achieves a 5.9× speedup over Icarus Verilog on an AES gate-level circuit, operates only 30% slower than Verilator while offering superior timing accuracy, and successfully recovers cryptographic keys via differential power analysis at both RTL and gate levels.
📝 Abstract
Designing hardware circuits resistant to side-channel attacks increasingly relies on simulation to predict device leakage before fabrication. Current functional verification simulators are designed for extended correctness-checking runs and are ill-suited for producing large numbers of short trace collections with slight input variants needed for side-channel analysis. We present Vogls: an open-source Verilog simulator built for side-channel analysis, that is the first simulator to combine compiled-code performance, full-timing simulation, and fine-grained control over the simulation state. Vogls simulates a timing annotated gate-level AES design 5.9 times faster than Icarus Verilog and is only 30% slower than Verilator on a PicoRV32 RTL design while also offering a more accurate timing model. Vogls provides a Python interface that allows simulations to be paused, forked, inspected, and mutated around points-of-interest without modifying the hardware design and thereby preserving timing and leakage characteristics. Furthermore, a trace-collection workflow runs setup code once and forks at the point-of-interest, eliminating the need to re-simulate from reset for every trace. A case study demonstrates Vogls on a differential power analysis attack that successfully recovers the key at RTL, GTL and full-timing GTL abstraction levels.