RTL-Sequencer: Towards Scalable RTL Timing Prediction with the Sequence-based Paradigm

2026-07-17

AI Summary

This work addresses the limitations of existing graph-based methods for register-transfer-level (RTL) timing prediction—namely, restricted receptive fields, high computational complexity, and neglect of signal directionality—by introducing a novel sequence modeling paradigm. The approach linearizes logic cones into ordered sequences via breadth-first traversal and integrates four key techniques: bidirectional attention, differentiable modeling, sequence shuffling, and a hybrid graph-sequence architecture. These innovations effectively capture both circuit topology and signal propagation characteristics. Experimental results demonstrate that the proposed method significantly outperforms state-of-the-art baselines, delivering more accurate and scalable timing predictions at early design stages and thereby substantially advancing RTL timing optimization capabilities.

Abstract

Accurate timing prediction at the register-transfer level (RTL) is a longstanding challenge in design automation. Existing graph-based methods struggle with limited receptive fields, high complexity, and a lack of signal directionality. We present RTL-Sequencer, a novel sequence-based paradigm that enables scalable RTL timing prediction via linearizing logic cones by breadth-first traversal and applying modern linear sequence models. Furthermore, sequence models are customized by four synergistic techniques, including sequence shuffling, bidirectional modeling, differentiable modeling, and a hybrid graph-sequence architecture. Extensive experiments demonstrate significant improvements of RTL-Sequencer over state-of-the-art baselines, advancing early-stage timing optimization.

Problem

• RTL timing prediction
• design automation
• timing analysis
• register-transfer level

Innovation

• sequence-based modeling
• RTL timing prediction
• linearized logic cones
• bidirectional modeling
• hybrid graph-sequence architecture