Strict-Priority Packet Delay in Switches with Transmit-Ring Buffering

2026-06-08

AI Summary

This work addresses a critical limitation in existing latency models for strict-priority scheduling, which neglect the impact of the transmit ring buffer (TXR) at switch egress ports, leading to inaccurate delay estimates for high-priority packets. For the first time, this study incorporates TXR into the end-to-end delay analysis framework by proposing a method to measure TXR size and integrating deterministic and stochastic modeling, network measurements, and hardware behavior characterization. The resulting model significantly improves the accuracy of both worst-case delay bounds and delay distribution predictions for high-priority traffic. Validated across multiple commercial off-the-shelf switches, the approach effectively bridges the gap between theoretical models and real hardware behavior, thereby enhancing the reliability of real-time network system design.

Abstract

Strict Priority (SP) scheduling is widely used at switch egress to provide low-latency service to high-priority (HP) traffic. Existing deterministic and stochastic latency models typically account for scheduler behavior and packet transmission, but omit a common switch implementation detail: the transmit ring (TXR) between the scheduler and the physical port. Because the switch must prepare the next packet before the current transmission completes, packets already placed in the TXR can further delay HP packets. This changes both the worst-case delay and the per-hop delay distribution of HP packets. This paper identifies this modeling gap, extends standard SP latency models to include the TXR, and validates the revised model through measurements on multiple switches. It also provides a measurement method for estimating the TXR size, a parameter that is often not reported in switch datasheets. The resulting model provides a closer representation of switch behavior for systems that use SP scheduling and require either delay bounds or delay distributions.

Problem

• Strict Priority
• Packet Delay
• Transmit Ring
• Switch Scheduling
• Latency Modeling

Innovation

• Strict Priority scheduling
• Transmit Ring buffering
• packet delay modeling
• worst-case delay
• switch measurement