A Spatio-Temporal Graph Neural Networks Approach for Predicting Silent Data Corruption inducing Circuit-Level Faults

2025-09-07

AI Summary

Accurately predicting the Fault Impact Probability (FIP) of Silent Data Errors (SDEs) caused by zero-time defects and aging in large sequential circuits remains challenging due to high computational costs of functional simulation-based approaches. Method: This paper proposes a fast, high-accuracy FIP prediction method based on a Spatio-Temporal Graph Convolutional Network (ST-GCN). It models gate-level netlists as spatio-temporal graphs, jointly encoding circuit topology (spatial structure) and multi-cycle signal evolution (temporal dynamics), while enabling end-to-end integration of testability metrics or fault-simulation features. Contribution/Results: The method drastically reduces reliance on expensive functional test simulations. Evaluated on the ISCAS-89 benchmarks, it achieves over 10× speedup versus conventional simulation-based methods, with a mean absolute error of only 0.024 for five-cycle FIP prediction. It notably enhances quantitative assessment of long-cycle, hard-to-detect faults and supports optimized test strategy design.

Technology Category

• Machine Learning: Probabilistic Circuits and Graphical Models
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Data Mining & Knowledge Management: Mining of Spatial, Temporal or Spatio-Temporal Data

Application Category

• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Security and Privacy: Large-scale security measurements
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics

Abstract

Silent Data Errors (SDEs) from time-zero defects and aging degrade safety-critical systems. Functional testing detects SDE-related faults but is expensive to simulate. We present a unified spatio-temporal graph convolutional network (ST-GCN) for fast, accurate prediction of long-cycle fault impact probabilities (FIPs) in large sequential circuits, supporting quantitative risk assessment. Gate-level netlists are modeled as spatio-temporal graphs to capture topology and signal timing; dedicated spatial and temporal encoders predict multi-cycle FIPs efficiently. On ISCAS-89 benchmarks, the method reduces simulation time by more than 10x while maintaining high accuracy (mean absolute error 0.024 for 5-cycle predictions). The framework accepts features from testability metrics or fault simulation, allowing efficiency-accuracy trade-offs. A test-point selection study shows that choosing observation points by predicted FIPs improves detection of long-cycle, hard-to-detect faults. The approach scales to SoC-level test strategy optimization and fits downstream electronic design automation flows.

Problem

• Predicting Silent Data Corruption from circuit-level faults
• Reducing expensive functional testing simulation time
• Enabling scalable quantitative risk assessment in large circuits

Innovation

• Spatio-temporal graph neural networks predict fault probabilities
• Models gate-level netlists as spatio-temporal graphs
• Reduces simulation time 10x while maintaining accuracy