GRAMC: General-purpose and reconfigurable analog matrix computing architecture

2025-01-03

AI Summary

Existing analog in-memory computing (AMC) architectures based on resistive random-access memory (RRAM) suffer from limited generality, supporting only single-purpose workloads due to fixed interconnect topologies between memory arrays and analog compute units. Method: This paper proposes a reconfigurable RRAM-based analog compute macro that enables dynamic reconfiguration of the interconnect topology between the storage array and analog amplifiers. It integrates on-chip write-and-verify calibration, mixed-signal co-design, and digital control logic to support diverse computational primitives. Contribution/Results: To the best of our knowledge, this is the first unified AMC architecture capable of executing general matrix multiplication, convolution, and matrix inversion within a single hardware substrate. By breaking the constraint of static topologies, it enables real-time task switching while achieving significantly higher energy efficiency and lower latency than state-of-the-art digital accelerators. The design establishes a scalable hardware paradigm for high-efficiency, multi-functional analog in-memory computing.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: (Computational) Cognitive Architectures
• Search and Optimization: Sampling/Simulation-based Search

Application Category

• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Economics, Online Markets and Human Computation: Architectures and workflows that use LLMs for crowd work

Abstract

In-memory analog matrix computing (AMC) with resistive random-access memory (RRAM) represents a highly promising solution that solves matrix problems in one step. However, the existing AMC circuits each have a specific connection topology to implement a single computing function, lack of the universality as a matrix processor. In this work, we design a reconfigurable AMC macro for general-purpose matrix computations, which is achieved by configuring proper connections between memory array and amplifier circuits. Based on this macro, we develop a hybrid system that incorporates an on-chip write-verify scheme and digital functional modules, to deliver a general-purpose AMC solver for various applications.

Problem

• Reconfigurable Computing
• Matrix Operations
• Flexibility in Circuit Design

Innovation

• Reconfigurable Circuit Block
• Matrix Computations
• Hybrid System Integration