TreeLUT: An Efficient Alternative to Deep Neural Networks for Inference Acceleration Using Gradient Boosted Decision Trees

2025-01-02

AI Summary

To address the high resource consumption and inference latency of deep neural networks for tabular data classification on FPGA edge devices, this paper proposes a fully LUT-mapped, quantized gradient-boosted decision tree (GBDT) hardware acceleration methodology. Departing from conventional approaches, it eliminates reliance on block RAMs (BRAMs) and digital signal processors (DSPs), implementing the entire tree structure natively using only lookup tables (LUTs). We introduce a custom fixed-point quantization scheme and a deeply pipelined tree traversal mechanism, enabling the first high-level synthesis (HLS) framework for GBDT that requires zero dedicated memory or multipliers—implemented atop Vivado. Evaluated across multiple benchmark datasets, our design achieves 3.2–8.7× smaller area, 2.1–5.4× lower latency, and 3.6–9.3× higher throughput compared to state-of-the-art FPGA-oriented frameworks—including DWN, FINN, and hls4ml—while preserving state-of-the-art classification accuracy.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Learning to Search
• Natural Language Processing: Learning & Optimization for NLP

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking
• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems

Abstract

Accelerating machine learning inference has been an active research area in recent years. In this context, field-programmable gate arrays (FPGAs) have demonstrated compelling performance by providing massive parallelism in deep neural networks (DNNs). Neural networks (NNs) are computationally intensive during inference, as they require massive amounts of multiplication and addition, which makes their implementations costly. Numerous studies have recently addressed this challenge to some extent using a combination of sparsity induction, quantization, and transformation of neurons or sub-networks into lookup tables (LUTs) on FPGAs. Gradient boosted decision trees (GBDTs) are a high-accuracy alternative to DNNs in a wide range of regression and classification tasks, particularly for tabular datasets. The basic building block of GBDTs is a decision tree, which resembles the structure of binary decision diagrams. FPGA design flows are heavily optimized to implement such a structure efficiently. In addition to decision trees, GBDTs perform simple operations during inference, including comparison and addition. We present TreeLUT as an open-source tool for implementing GBDTs using an efficient quantization scheme, hardware architecture, and pipelining strategy. It primarily utilizes LUTs with no BRAMs or DSPs on FPGAs, resulting in high efficiency. We show the effectiveness of TreeLUT using multiple classification datasets, commonly used to evaluate ultra-low area and latency architectures. Using these benchmarks, we compare our implementation results with existing DNN and GBDT methods, such as DWN, PolyLUT-Add, NeuraLUT, LogicNets, FINN, hls4ml, and others. Our results show that TreeLUT significantly improves hardware utilization, latency, and throughput at competitive accuracy compared to previous works.

Problem

• Complex Brain Network Decision-making
• Efficient Resource Consumption
• Table Data Classification and Prediction

Innovation

• TreeLUT
• FPGA-based GBDT
• Quantization and Hardware Design