QUADOL: A Quality-Driven Approximate Logic Synthesis Method Exploiting Dual-Output LUTs for Modern FPGAs

2024-11-27

arXiv.org

AI Summary

Existing FPGA-based approximate computing research achieves area optimization via dual-output LUTs (DO-LUTs) only for small-scale arithmetic circuits, lacking scalability to general large-scale designs. This work proposes a quality-driven approximate logic synthesis (ALS) methodology: it introduces, for the first time, LUT-pair approximation merging as a new optimization dimension—merging two single-output LUTs into one DO-LUT—and formulates the problem as maximum matching to maximize area reduction. The approach is fully compatible with and augmentable by any existing ALS technique. We further design QUADOL+, a generic integration framework enabling seamless deployment across diverse approximate circuit families. Experimental evaluation demonstrates up to 18% LUT count reduction. Moreover, QUADOL+ achieves superior Pareto-optimal trade-offs between area savings and approximation error compared to state-of-the-art FPGA-based approximate multipliers.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Learning to Search
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories

Application Category

• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications

Abstract

Approximate computing is a new computing paradigm. One important area of it is designing approximate circuits for FPGA. Modern FPGAs support dual-output LUT, which can significantly reduce the area of FPGA designs. Several existing works explored the use of dual-output in approximate computing. However, they are limited to small-scale arithmetic circuits. To address the problem, this work proposes QUADOL, a quality-driven ALS method by exploiting dual-output LUTs for modern FPGAs. We propose a technique to approximately merge two single-output LUTs (i.e., a LUT pair) into a dual-output LUT. In addition, we transform the problem of selecting multiple LUT pairs for simultaneous approximate merging into a maximum matching problem to maximize the area reduction. Since QUADOL exploits a new dimension, i.e., approximately merging a LUT pair into a dual-output LUT, it can be integrated with any existing ALS methods to strengthen them. Therefore, we also introduce QUADOL+, which is a generic framework to integrate QUADOL into existing ALS methods. The experimental results showed that QUADOL+ can reduce the LUT count by up to 18% compared to the state-of-the-art ALS methods for FPGA. Moreover, the approximate multipliers optimized by QUADOL+ dominate most prior FPGA-based approximate multipliers in the area-error plane.

Problem

• Exploiting dual-output LUTs for FPGA approximate computing
• Addressing limitations to small-scale arithmetic circuits
• Maximizing area reduction through approximate LUT merging

Innovation

• Approximate merging of LUT pairs into dual-output LUTs
• Transforming LUT pair selection into maximum matching problem
• Integrating QUADOL with existing ALS methods via QUADOL+ framework