π€ AI Summary
This work addresses the challenges of high-resolution PCB defect detection, where naive global resizing often loses minute defects, while standard tiling-based inference introduces boundary artifacts that cause false negatives and positives. To overcome these issues, the authors propose a training-free, model-agnostic post-processing method termed Topology-Aware Tile Merging (TA-TM). Leveraging 640Γ640 tiles with 128-pixel overlaps, TA-TM constructs an adjacency graph to dynamically adjust detection scores near tile boundaries and refines results via global non-maximum suppression. Evaluated on the PCB-Defect and HRIPCB datasets, the approach achieves mAP@50 of 0.72 and 0.94, respectively, boosts boundary-region recall to 70β100%, and recovers 46β100% of small defects missed by full-image methods.
π Abstract
High-resolution printed circuit board (PCB) inspection suffers from resolution collapse when full-board images are resized to standard detector inputs: micro-scale defects shrink to a few pixels and are missed. Tile-based inference preserves local detail but introduces boundary artefacts at tile edges, causing split detections and false negatives. We present a systematic comparison of five inference strategies evaluated on two high-resolution PCB defect datasets, PCB-Defect (230 images, 1704 annotations) and HRIPCB (693 images, 2 953 annotations), spanning six defect classes. We show that training-inference scale consistency is critical: a detector trained on full images collapses to mAP@50 = 0.01 under tile inference, while the same architecture trained on 640*640 tile crops achieves 0.72 and 0.94 on the two datasets respectively. We further exploited Topology-Aware Tile Merging (TA-TM), a training-free post-processing method that builds a tile-adjacency graph and adjusts boundary-sensitive detection scores using neighbour-tile agreement before global NMS. Across both datasets, adding 128 px tile overlap raises boundary-zone recall from ~26-63% to ~70-100%, TA-TM achieves the best mAP@50 on both benchmarks, and tile inference recovers 46-100% of small defects missed entirely by full-image methods. Results are consistent across datasets, confirming the generalizability of the proposed strategy. TA-TM requires no retraining and is architecture-agnostic, making it directly applicable to existing PCB inspection pipelines.